UPI-452 Datasheet, PDF (25/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
The FIFO IN COMMAND IN and Immediate Com-
mand In SFRs are read only registers Any write op-
eration performed on these registers will be ignored
and the FIFO pointers will remain intact
The internal CPU uses the FIFO OUT SFR to write
to the Output FIFO and any instruction which uses
the FIFO OUT or COMMAND OUT SFR as a desti-
nation will invoke a FIFO write DSCs are differenti-
ated from data by writing to the COMMAND OUT
SFR In the FIFO Data Stream Commands have the
ninth bit associated with the command byte set to
‘‘1’’ The instructions used to write to the Output
FIFO are listed below
MOV FIFO OUT COMMOUT A
MOV FIFO OUT COMMOUT direct
MOV FIFO OUT COMMOUT Rn
POP FIFO OUT COMMOUT
MOV FIFO OUT COMMOUT data
MOV FIFO OUT COMMOUNT Ri
NOTE
Instructions which use the FIFO OUT COMMAND
OUT SFRs as both a source and destination regis-
ter cause invalid data to be written into the Output
FIFO These instructions are not supported by the
UPI-452 FIFO
GENERAL PURPOSE DMA CHANNELS
dress Register (DAR) (Note Since the FIFO IN SFR
is a read only register the DMA transfer will be ig-
nored if it is used as a DMA DAR This is also true if
the FIFO OUT SFR is used as a DMA SAR )
Each DMA channel is software programmable to op-
erate in either Block Mode or Demand Mode In the
Block Mode DMA transfers can be further pro-
grammed to take place in Burst Mode or Alternate
Cycle mode In Burst Mode the processor halts its
execution and dedicates its resources to the DMA
transfer In Alternate Cycle Mode DMA cycles and
instruction cycles occur alternately
In Demand Mode a DMA transfer occurs only when
it is demanded Demands can be accepted from an
external device (through External Interrupt pins
EXT0 EXT1) or from either the Serial Channel or
FIFO flags In this way a DMA transfer can be syn-
chronized to an external device the FIFO or the Se-
rial Port If the External Interrupt is configured in
Edge Mode a single byte transfer occurs per tran-
sition The external interrupt itself will occur if en-
abled If the External Interrupt is configured in Level
Mode DMA transfers continue until the External In-
terrupt request goes inactive or the byte count be-
comes zero The following flags activate Demand
Mode transfers of one byte to from the FIFO or Seri-
al Channel
RI - Serial Channel Receiver Buffer Full
TI - Serial Channel Transmitter Buffer Empty
Overview
There are two identical General Purpose DMA Chan-
nels on the UPI-452 which allow high speed data
transfer from one writeable memory space to anoth-
er As many as 64K bytes can be transferred in a
single DMA operation The following memory
spaces can be used with DMA channels
 Internal Data Memory
 External Data Memory
 Special Function Registers
The Special Function Register array appears as a
limited group of dedicated memory addresses The
Special Function Registers may be used in DMA
transfer operations by specifying the SFR as the
source or destination address The Special Function
Registers which may be used in DMA transfers are
listed in Table 4 Table 4 also shows whether the
SFR may be used as Source or Destination only or
both
The FIFO can be accessed during DMA by using the
FIFO IN SFR as the DMA Source Address Register
(SAR) or the FIFO OUT SFR as the Destination Ad-
Architecture
There are three 16 bit and one 8 bit Special Function
Registers associated with each DMA channel
 The 16 bit Source Address SFR (SAR) points to
the source byte
 The 16 bit Destination Address SFR (DAR) points
to the destination
 The 16 bit Byte Count SFR (BCR) contains the
number of bytes to be transferred and is decre-
mented when a byte transfer is accomplished
 The DMA Control SFR (DCON) is eight bits wide
and specifies the source memory space destina-
tion memory space and the mode of operation
In Auto Increment mode the Source Address and
or Destination Address is incremented when a byte
is transferred When a DMA transfer is complete
(BCR ^e 0) the DONE bit is set and a maskable
interrupt is generated The GO bit must be set to
start any DMA transfer (also the Slave Control SFR
FRZ bit must be set to disable FIFO DMA Freeze
Mode) The two DMA channels are designated as
DMA0 and DMA1 and their corresponding registers
are suffixed by 0 or 1 e g SAR0 DAR1 etc
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