UPI-452 Datasheet, PDF (53/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
REVISION HISTORY
DOCUMENT
UPI-452 Data Sheet
OLD REVISION NUMBER
231428-005
NEW REVISION NUMBER 231428-006
1 Maximum Clock Rate was changed from 16 MHz to 14 MHz This change is reflected in all Maximum Timing
specifications
2 The proper range of values for ITHR has been changed from 0 to (CBP-2) to 0 to (CBP-3) to ensure
proper setting of the Input FIFO request for service bit See the following sections INPUT FIFO CHANNEL
and INPUT AND OUTPUT FIFO THRESHOLD SFR (ITHR OTHR)
3 The proper range of values for OTHR has been changed from 1 to (80H-CBP)-1 to 2 to (80-CBP)-1
to ensure proper setting of the Output FIFO request for service bit See the following sections OUTPUT
FIFO CHANNEL FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE and INPUT AND OUT-
PUT FIFO THRESHOLD SFR (ITHR OTHR)
4 The following D C Characteristics were deleted from the data sheet
V_OH ^e 0 75 V_CC I_OH ^{e b}25 mA
V_OH1 ^e 0 75 V_CC I_OH ^e 150 mA
V_OH2 ^e 3 0V I_OH ^e 1 mA and
I_CC1 ^e 15 mA V_CC ^e 5 5V (87C452P)
See D C CHARACTERISTICS TABLE
5 The parameter descriptions for THHAH and THLAL has been reversed and their maximum specification for
clock rates less than 14 MHz has been changed from 4TCLC ^a 100 ns to 8TCLC ^a 100 ns See
HLD HLDA TIMINGS
6 TAMIN specification has been removed from the Arbiter Mode waveform diagram and added to the Request-
or Mode waveform diagram See HLD HLDA WAVEFORMS
7 Minimum TDHR timing changed from 5 ns to 7 ns
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