UPI-452 Datasheet, PDF (36/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
The UPI-452 can also be programmed to interrupt
the Host following power on reset in order to indi-
cate to the Host that FIFO DMA Freeze Mode is in
progress This is done by enabling the INTRQ inter-
rupt output pin via the MODE SFR (MD4) before the
Slave Control SFR Enable FIFO DMA Freeze Mode
bit is set to Normal Mode At power on reset the
Mode SFR is forced to zero This disables all inter-
rupt and DMA output pins (INTRQ DRQIN
INTRQIN and DRQOUT INTRQOUT) Because the
Host Status SFR FIFO DMA Freeze Mode In Prog-
ress bit is set a Request For Service INTRQ inter-
rupt is pending until the Host Status SFR is read
This is because the FIFO DMA Freeze Mode inter-
rupt is always enabled If the Slave Control FIFO
DMA Freeze Mode bit (SLCON FRZ) is set to Nor-
mal Mode before the MODE SFR INTRQ bit is en-
abled the INTRQ output will not go active when the
MODE SFR INTRQ bit is enabled if the Host Status
SFR has been read
The default values for the FIFO and Slave Interface
represents minimum UPI-452 internal initialization
No specific Special Function Register initialization is
required to begin operation of the FIFO Slave Inter-
face The last initialization instruction must always
set the UPI-452 to Normal Mode This causes the
UPI-452 to exit FIFO DMA Freeze Mode and en-
ables Host read write access of the FIFO
Following reset either hardware (via the RST pin) or
software (via HCON SFR bit HC3) the UPI-452 re-
quires 2 internal machine cycles (24 TCLCL) to up-
date all internal registers
Invoking FIFO DMA Freeze Mode
During Normal Operation
When the UPI-452 is in normal operation FIFO DMA
Freeze Mode should not be arbitrarily invoked by
clearing SC3 (SC3^e0) because the external Host
runs asynchronously to the internal CPU Invoking
FIFO DMA Freeze Mode without first stopping the
external Host from accessing the UPI-452 will not
guarantee a clean break with the external Host
The proper way to invoke FIFO DMA Freeze Mode is
by issuing an Immediate Command to the external
host indicating that FIFO DMA Freeze Mode will be
invoked Upon receiving the Immediate Command
the external Host should complete servicing all
pending interrupts and DMA requests then send an
Immediate Command back to the UPI-452 acknowl-
edging the FIFO DMA Freeze Mode request After
issuing the first Immediate Command the internal
CPU should not perform any action on the FIFO until
FIFO DMA Freeze Mode is invoked
If FIFO DMA Freeze Mode is invoked without stop-
ping the Host during Host transfers only the last two
bytes of data written into or read from the FIFO will
be valid The timing diagram for disabling the FIFO
module to the external Host interface is illustrated in
Figure 12 Due to this synchronization sequence the
UPI-452 might not go into FIFO DMA Freeze Mode
immediately after SC3 is cleared A special bit in the
Slave Status Register (SST5) is provided to indicate
the status of the FIFO DMA Freeze Mode The FIFO
DMA Freeze Mode operations described in this sec-
tion are only valid after SST5 is cleared
As FIFO DMA Freeze Mode is invoked the DRQIN
or DRQOUT will be deactivated (stopping the trans-
ferring of data) bit 1 of the Host Status SFR will be
set (HST1^e1) and SST5 will be cleared (SST5^e0)
to indicate to the external Host and internal CPU
that the slave interface has been frozen After the
freeze becomes effective any attempt by the exter-
nal Host to access the FIFO will cause the overrun
and underrun bits to be activated (bits HST7 (for
reads) or HST3 (for writes)) These two bits HST3
and HST7 will be set (deactivated) after the Host
Status SFR has been read If INTRQ is used to re-
quest service the FIFO interface is frozen upon
completion of any Host read or write operation in
progress
231428 – 17
Figure 12 Disabling FIFO to Host Slave Interface Timing Diagram
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