UPI-452 Datasheet, PDF (38/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Label
HCON
HSTAT
SLCON
SSTAT
IEP
MODE
IWPR
IRPR
OWPR
ORPR
CBP
IMIN
IMOUT
FIN
CIN
FOUT
COUT
ITHR
OTHR
Table 9 FIFO SFR’s Characteristics During FIFO DMA Freeze Mode
Name
Normal
Operation
(SST5 ^e 1)
FIFO DMA Freeze Mode
Operation
(SST5 ^e 0)
Host Control
Not Accessible
Read Write
Host Status
Read Only
Read Write 4
Slave Control
Read Write
Read Write
Slave Status
Read Only
Read Write 4
Interrupt Enable Priority
Read Write
Read Write
Mode Register
Read Write
Read Write
Input FIFO Write Pointer
Read Only
Read Write 5
Input FIFO Read Pointer
Read Only
Read Write 1 5
Output FIFO Write Pointer
Read Only
Read Write 6
Output FIFO Read Pointer
Read Only
Read Write 2 6
Channel Boundary Pointer
Read Only
Read Write 3
Immediate Command In
Read Only
Read Write
Immediate Command Out
Read Write
Read Write
FIFO IN
Read Only
Read Only
COMMAND IN
Read Only
Read Only
FIFO OUT
Read Write
Read Write
COMMAND OUT
Read Write
Read Write
Input FIFO Threshold
Read Only
Read Write
Output FIFO Threshold
Read Only
Read Write
NOTES
1 Writing of IRPR will automatically cause the FIFO IN SFR to load the contents of the Input FIFO from that location
2 Writing to ORPR will automatically cause the IOBL SFR to load the contents of the Output FIFO at that ORPR address
3 Writing to the CBP SFR will cause automatic reset of the four pointers of the Input and Output FIFO channels
4 The internal CPU cannot directly change the status of these registers However by changing the status of the FIFO
channels the internal CPU can indirectly change the contents of the status registers
5 Changing the Input FIFO Read Write Pointers also requires that a consistent update of the Input FIFO Threshold Counter
SFR
6 Changing the Output FIFO Read Write Pointers also requires that a consistent update of the Output FIFO Threshold
Counter SFR
38