UPI-452 Datasheet, PDF (11/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Figure 4 UPI-452 Functional Block Diagram
231428 – 8
The division of the 128 bytes between Input and
Output channels is user programmable allowing
maximum flexibility If the entire 128 byte FIFO is
allocated to the Input channel a high performance
Host can transfer up to 128 bytes at one time then
dedicate its resources to other functions while the
internal CPU processes the data in the FIFO Vari-
ous handshake signals allow the external Host to
operate independently and without frequent monitor-
ing of the UPI-452 internal CPU The FIFO Buffer
insures that the slave processor receives data in the
same order that it was sent by the host without the
need to keep track of addresses Three slave bus
interface handshake methods are supported by the
UPI-452 DMA Interrupt and Polled
The FIFO is nine bits wide The ninth bit acts as a
command data flag Commands written to the FIFO
by either the host or internal CPU are called Data
Stream Commands or DSCs DSCs are written to
the input FIFO by the Host via a unique external
address DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Func-
tion Register (SFR) When encountered by the host
or internal CPU a Data Stream Command can be
used as an address vector to user defined service
routines DSCs provide synchronization of data and
commands between the Host and internal CPU
FIFO PROGRAMMABLE FEATURES
Size of Input Output Channels
The 128 bytes of FIFO space can be allocated be-
tween the Input and Output channels via the Chan-
nel Boundary Pointer (CBP) SFR This register con-
tains the number of address locations assigned to
the Input channel The remaining address locations
are automatically assigned to the Output FIFO The
CBP SFR can only be programmed by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-Ex-
ternal Host Interface FIFO DMA Freeze Mode de-
scription) The CBP is initialized to 40H (64 bytes)
upon reset
The number in the Channel Boundary Pointer SFR is
actually the first address location of the Output
FIFO Writing to the CBP SFR reassigns the Input
and Output FIFO address space Whenever the CBP
is written the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
the CBP SFR
All of the FIFO space may be assigned to one chan-
nel In such a situation the other channel’s data path
consists of a single SFR (FIFO IN COMMAND IN or
FIFO OUT COMMAND OUT SFR) location
CBP
Register
0
1
2
3
4

7B
7C
7D
7E
7F
Input FIFO
Size
1
1
2
3
4

123
124
125
128
128
Output FIFO
Size
128
128
126
125
124

5
4
3
1
1
11