UPI-452 Datasheet, PDF (22/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
HST7 Output FIFO Underrun Error Condition
1 ^e No Underrun Error
0 ^e Underrun Error (latched until Host
Status Register is read)
HST6 Immediate Command Out SFR Status
1 ^e Empty
0 ^e Immediate Command Present
HST5 Data Stream Command Data at Output
FIFO Status
1 ^e Data (not DSC)
0 ^e DSC (present at Output FIFO COM-
MAND OUT SFR)
(Note Only if HST4^e0 if HST4^e1 then un-
determined)
HST4 Output FIFO Request for Service Status
1 ^e No Request for Service
0 ^eOutput FIFO Request for Service due to
a Output FIFO containing the threshold
number of bytes or more
b Internal CPU sending a block of data ter-
minated by a DSC (DSC Flush Mode)
HST3 Input FIFO Overrun Error Condition
1 ^e No Overrun Error
0 ^e Overrun Error (latched until Host Status
Register is read)
HST2 Immediate Command In SFR Status
1 ^e Full (i e Internal CPU has not read pre-
vious Immediate Command sent by Host)
0 ^e Empty
Reset value
‘1’ if read by the external Host
‘0’ if read by internal CPU (reads shadow
latch - see FIFO DMA Freeze Mode descrip-
tion)
HST1 FIFO DMA Freeze Mode Status
1 ^e Freeze Mode in progress
(In Freeze Mode the bits of the Host Status
SFR are forced to a ‘1’ initially to prevent the
external Host from attempting to access the
FIFO The definition of the Host Status SFR
bits during FIFO DMA Freeze Mode can be
found in FIFO DMA Freeze Mode descrip-
tion)
0 ^e Normal Operation
HST0 Input FIFO Request Service Status
1 ^e Input FIFO does not request service
0 ^e Input FIFO request service due to the
Input FIFO containing enough space for the
host to write the threshold number of bytes
or more
22
FIFO MODULE - EXTERNAL HOST
INTERFACE
Overview
The FIFO-external Host interface supports high
speed asynchronous bi-directional 8-bit data trans-
fers The host interface is fully compatible with Intel
microprocessor local busses and with MULTIBUS
The FIFO has two specialized DMA request pins for
Input and Output FIFO channel DMA requests
These are multiplexed to provide a dedicated Re-
quest for Service interrupt (DRQIN INTRQIN
DRQOUT INTRQOUT)
The external Host can program under user defined
protocol thresholds into the FIFO Input and Output
Threshold SFRs which determine when the FIFO
Request for Service interrupt is generated to the
Host CPU The FIFO module external Host interface
is configured by the internal CPU via the MODE
SFR ‘‘The external Host can enable and disable
Host interface interrupts via the Host Control SFR ’’
Data Stream Commands in the Input FIFO channel
allow the Host to influence the processing of data
blocks and are sent with the data flow to maintain
synchronization Data Stream Commands in the
Output FIFO Channel allow the internal CPU to per-
form the same function and also to set the Output
FIFO Request Service status logic to the host CPU
regardless of the programmed value in the Thresh-
old SFR
Slave Interface Address Decoding
The UPI-452 determines the desired Host function
through address decoding The lower three bits of
the address as well as the READ WRITE Chip Se-
lect (CS) and DMA Acknowledge (DACK) are used
for decoding Table 3 shows the pin states and the
Read or Write operations associated with each con-
figuration
Interrupts to the Host
The UPI-452 interrupts the external Host via the
INTRQ pin In addition the DRQIN and DRQOUT
pins can be multiplexed as interrupt request lines
INTRQIN and INTRQOUT respectively when DMA
is disabled This provides two special FIFO ‘‘Re-
quest for Service’’ interrupts
There are eight FIFO-related interrupt sources two
from The Input FIFO three from The Output FIFO
one from the Immediate Command Out SFR one
from the Immediate Command IN SFR and one due
to FIFO DMA Freeze Mode
INPUT FIFO The Input FIFO interrupt is generated
whenever
a The Input FIFO contains space for a threshold
number of bytes