UPI-452 Datasheet, PDF (23/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Table 3 UPI-452 Address Decoding
DACK CS A2 A1 A0
Read
Write
1 1 X X X No Operation
No Operation
1 0 0 0 0 Data or DMA from Output FIFO Channel
Data or DMA to Input FIFO Channel
1 0 0 0 1 Data Stream Command from Output FIFO Channel Data Stream Command to Input FIFO Channel
1 0 0 1 0 Host Status SFR Read
Reserved
1 0 0 1 1 Host Control SFR Read
Host Control SFR Write
1 0 1 0 0 Immediate Command SFR Read
Immediate Command to SFR Write
1 0 1 1 X Reserved
Reserved
0 X X X X DMA Data from Output FIFO Channel
DMA Data to Input FIFO Channel
1 0 1 0 1 Reserved
Reserved
NOTES
1 Attempting to read a DSC as a data byte will result in invalid data being read The read pointers are not incremented so
that the DSC is not lost Attempting to read a data byte as a DSC has the same result
2 If DACK is active the UPI-452 will attempt a DMA operation when RD or WR becomes active regardless of the DMA
enable bit (MD6) in the MODE SFR Care should be taken when using DACK For proper operation DACK must be driven
high (a5V) when not using DMA
b When an Input FIFO overrun error condition ex-
ists The appropriate bits in the Host Status SFR
are set and the interrupt is generated only if en-
abled
OUTPUT FIFO The Output FIFO Request for Serv-
ice Interrupt operates in a similar manner as the In-
put FIFO interrupt
a When the FIFO contains the threshold number of
bytes or more
b Output FIFO error condition interrupts are gener-
ated when the Output FIFO is underrun
c Data Stream Command present in the Output
Buffer Latch
A Data Stream Command interrupt is used to halt
normal processing using the command as a vector
to a service routine When DMA is disabled the user
may program (through HC1) INTRQ to include FIFO
Request for Service Interrupts or use INTRQIN and
INTRQOUT as Request for Service Interrupts
IMMEDIATE COMMAND INTERRUPTS
a An Immediate Command Out Interrupt is generat-
ed if enabled to the Host and the corresponding
Host Status SFR bit (HSTAT HST6) is cleared
when the internal CPU writes to the Immediate
Command OUT (IMOUT) SFR When the Host
reads the Immediate Command OUT (IMOUT)
SFR the corresponding bit in the Host Status
(HSTAT) SFR is set This causes the Slave Status
Immediate Command OUT Status bit (SSTAT
SST6) to be cleared indicating that the Immediate
Command OUT (IMOUT) SFR is empty If en-
abled a FIFO-Slave Interface will also be gener-
ated to the internal CPU (See Figure 7b Immedi-
ate Command OUT Flowchart )
b An Immediate Command IN interrupt is generat-
ed if enabled to the Host when the internal CPU
has read a byte from the Immediate Command IN
(IMIN) SFR The read operation clears the Host
Status SFR Immediate Command IN Status bit
(HSTAT HST2) indicating that the Immediate
Command IN SFR is empty The corresponding
Slave Status (SSTAT) SFR bit is also set to indi-
cate an empty status Setting the Slave Status
SFR bit generates a FIFO-Slave Interface inter-
rupt if enabled to the internal CPU (See Figure
7a Immediate Command IN Flowchart )
NOTE
Immediate Command IN and OUT interrupts are ac-
tually specific Request For Service interrupts to the
Host
FIFO DMA FREEZE MODE When the internal CPU
invokes FIFO DMA Freeze Mode for example at re-
set or to reconfigure the FIFO interface INTRQ is
activated The INTRQ can only be deactivated by
the external Host reading the Host Status SFR
(HST1 remains active until FIFO DMA Freeze Mode
is disabled by the internal CPU)
Once an interrupt is generated INTRQ will remain
high until no interrupt generating condition exists
For a FIFO underrun overrun error interrupt the in-
terrupt condition is deactivated by the external Host
reading the Host Status SFR An interrupt is serv-
iced by reading the Host Status SFR to determine
the source of the interrupt and vectoring the appro-
priate service routine
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