UPI-452 Datasheet, PDF (10/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
UPI-452 PIN DESCRIPTIONS (Continued)
Symbol
Pin
Type
Name and Function
INTRQ
50
O This output pin is used to interrupt the host processor when an
Immediate Command Out or an error condition is encountered It is
also used to interrupt the host processor when the FIFO requests
service if the DMA is disabled and INTRQIN and INTRQOUT are
not used
DACK
45
I
This pin is the DMA acknowledge for the host bus interface Input
and Output Channels When activated a write command will cause
the data on the Slave Data Bus to be written as data to the Input
Channel (to the Input FIFO) A read command will cause the Output
Channel to output data (from the Output FIFO) on to the Slave Data
Bus This pin should be driven high (^a5V) in systems which do not
have a DMA controller (see Address Decoding)
V_CC
26
I
a_{5V power supply during operation}
ARCHITECTURAL OVERVIEW
Introduction
The UPI-452 slave microcontroller incorporates an
80C51 with double the program and data memory a
slave interface which allows it to be connected di-
rectly to the host system bus as a peripheral a FIFO
buffer module a two channel DMA processor and a
fifth I O port (Figure 3) The UPI-452 retains all of
the 80C51 architecture and is fully compatible with
the MCS-51 instruction set
The Special Function Register (SFR) interface con-
cept introduced in the MCS-51 family of microcon-
trollers has been expanded in the UPI-452 To the
20 Special Function Registers of the MCS-51 the
UPI-452 adds 34 more These additional Special
Function Registers like those of the MCS-51 pro-
vide access to the UPI-452 functional elements in-
cluding the FIFO DMA and added interrupt capabili-
ties Several of the 80C51 core Special Function
Registers have also been expanded to support add-
ed features of the UPI-452
This data sheet describes the unique features of the
UPI-452 Refer to the 80C51 data sheet for a de-
scription of the UPI-452’s core CPU functional
blocks including
Timers Counters
I O Ports
Interrupt timing and control (other than FIFO and
DMA interrupts)
Serial Channel
Local Expansion Bus
Program Data Memory structure
Power-Saving Modes of Operation
CHMOS Features
Instruction Set
Figure 3 contains a conceptual block diagram of the
UPI-452 Figure 4 provides a functional block dia-
gram
FIFO Buffer Interface
A unique feature of the UPI-452 is the incorporation
of a 128 byte FIFO array at the host-slave interface
The FIFO allows asynchronous bi-directional trans-
fers between the host CPU and the internal CPU
Figure 3 UPI-452 Conceptual Block Diagram
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