UPI-452 Datasheet, PDF (27/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
DONE DMA transfer Flag
0 DMA transfer is not completed
1 DMA transfer is complete
NOTE
This flag is set when contents of the Byte Count
SFR decrements to zero It is reset automatically
when the DMA vectors to its interrupt routine
GO
Enable DMA Transfer
0 Disable DMA transfer (in all modes)
1 Enable DMA transfer If the DMA is in
the Block mode start DMA transfer if
possible If it is in the Demand mode
enable the channel and wait for a de-
mand
NOTE
The GO bit is reset when the BCR decrements to
zero
DMA Transfer Modes
The following four modes of DMA operation are pos-
sible in the UPI-452
1 ALTERNATE-CYCLE MODE
General
Alternate cycle mode is useful when CPU process-
ing must occur during the DMA transfers In this
mode a DMA cycle and an instruction cycle occur
alternately The interrupt request is generated (if en-
abled) at the end of the process i e when BCR dec-
rements to zero The transfer is initiated by setting
the GO bit in the DCON SFR
Alternate-Cycle FIFO Demand Mode
Alternate cycle demand mode is useful for FIFO
transfers of a less urgent nature As mentioned be-
fore CPU instruction cycles are interleaved with
DMA transfer cycles allowing true parallel process-
ing
This mode differs from FIFO Demand Mode in that
CPU instruction cycles must be interleaved with
DMA transfers even if the FIFO is demanding DMA
In FIFO Demand Mode CPU cycles would never oc-
cur if the FIFO demand was present
Input Channel
The DMA is configured as in FIFO Demand Mode
and transfers are initiated whenever an Input FIFO
service request is generated DMA transfer cycles
are alternated with instruction execution cycles
DMA transfers are terminated as in FIFO Demand
Mode
Output Channel
The DMA is configured as in FIFO Demand Mode
and transfers are initiated whenever an Output FIFO
requests service DMA transfer cycles are alternated
with instruction execution cycles DMA transfers are
terminated as in FIFO Demand Mode
The FIFO logic resets the interrupt flag after trans-
ferring the byte so the interrupt is never generated
Once the DMA is programmed to service the FIFO
the request for service interrupt for the FIFO is inhib-
ited until the DMA is done (BCR ^e 0)
2 BURST MODE
In BURST mode the DMA is initiated by setting the
GO bit in the DCON SFR The DMA operation con-
tinues until BCR decrements to zero (zero byte
count) then an interrupt is generated (if enabled)
No interrupts are recognized during this DMA opera-
tion once it has started
Input Channel
The FIFO Input Channel can be used in burst mode
by specifying the FIFO IN SFR as the DMA Source
Address DMA transfers begin when the GO bit in
the DMA Control SFR is set The number of bytes to
be transferred must be specified in the Byte Count
SFR (BCR) and auto-incrementing of the SAR must
be disabled Once the GO bit is set nothing can in-
terrupt the transfer of data until the BCR is zero In
this mode a Data Stream Command encountered in
the FIFO will be held in the COMMAND IN SFR with
the pointers frozen and invalid data (FFH) will be
read through the FIFO IN SFR If the input FIFO
becomes empty during the block transfer an 0FFH
will be read until BCR decrements to zero
Output Channel
The Output FIFO Channel can be used in burst
mode by specifying the FIFO OUT or COMMAND
OUT SFR as the DMA Destination Address DMA
transfers begin when the GO bit is set This mode
can be used to send a block of data or a block of
Data Stream Commands If the FIFO becomes full
during the block transfer the remaining data will be
lost
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