UPI-452 Datasheet, PDF (35/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
FIFO-EXTERNAL HOST INTERFACE
FIFO DMA FREEZE MODE
Overview
During FIFO DMA Freeze Mode the internal CPU
can reconfigure the FIFO interface FIFO DMA
Freeze Mode is provided to prevent the Host from
accessing the FIFO during a reconfiguration se-
quence The internal CPU invokes FIFO DMA
Freeze Mode by clearing bit 3 of the Slave Control
SFR (SC3) INTRQ becomes active whenever FIFO
DMA Freeze Mode is invoked to indicate the freeze
status The interrupt can only be deactivated by the
Host reading the Host Status SFR
During FIFO DMA Freeze Mode only two operations
are possible by the Host to the UPI-452 slave the
balance are disabled as shown in Table 8 The in-
ternal DMA is disabled during FIFO DMA Freeze
Mode and the internal CPU has write access to all
of the FIFO control SFRs (Table 9)
Initialization
At power on reset the FIFO Host interface is auto-
matically frozen The Slave Control Enable FIFO
DMA Freeze Mode bit defaults to FIFO DMA Freeze
Mode (SLCON FRZ^e0) Below is a list of the FIFO
Special Function Registers and their default power
on reset values
SFR Name
Label Value
Channel Boundary Pointer CBP 40H 64D
Output Channel Read Pointers ORPR 40H 64D
Output Channel Write Pointers OWPR 40H 64D
Input Channel Read Pointers IRPR 00H 00D
Input Channel Write Pointers IWPR 00H 00D
Input Threshold
ITHR 80H 128D
Output Threshold
OTHR 01H 1D
The Input and Output FIFO channels can be recon-
figured by programming any of these SFRs while the
UPI-452 is in the Freeze Mode The Host is notified
when the Freeze Mode is active by a ‘‘1’’ in HST1 of
the Host Status Register (HSTAT) The Host should
interrogate HST1 to determine the status of the
FIFO interface following reset before attempting to
read from or write to the UPI-452 FIFO buffer
NOTE
During the initialization sequence of the UPI-452
FIFO SFRs the OTHR should be changed from the
default setting of 1 to a value between 2 and
(80H-CBP)-1 Please refer to the section on Input
and Output FIFO threshold SFRs for further infor-
mation
Table 8 Slave Bus Interface Status During FIFO DMA Freeze Mode
Interface Pins
DACK
CS A2 A1 A0 READ WRITE
Operation In
Normal Mode
Status In
FIFO DMA Freeze Mode
1
0010 0
1 Read Host Status SFR
Operational
1
0011 0
1 Read Host Control SFR
Operational
1
0011 1
0 Write Host Control SFR
Disabled
1
0000 0
1 Data or DMA Data from
Disabled
Output Channel
1
0000 1
0 Data or DMA Data to
Disabled
Input Channel
1
0001 0
1 Data Stream Command from Disabled
Output Channel
1
0001 1
0 Data Stream Command to Disabled
Input Channel
1
0100 0
1 Read Immediate Command Disabled
Out from Output Channel
1
0100 1
0 Write Immediate Command Disabled
In to Input Channel
0
XXXX 0
1 DMA Data from Output
Disabled
Channel
0
XXXX 1
0 DMA Data to Input Channel Disabled
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