UPI-452 Datasheet, PDF (14/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
The host CPU writes data and Data Stream Com-
mands into the Input Buffer Latch on the rising edge
of the external WR signal External addressing de-
termines whether the byte is a data byte or Data
Stream Command and the FIFO logic sets the ninth
bit of the FIFO accordingly as the byte is moved
from the Input Buffer Latch into the FIFO A ‘‘1’’ in
the ninth bit indicates that the incoming byte is a
Data Stream Command The internal CPU reads
data bytes via the FIFO IN SFR and Data Stream
Commands via the COMMAND IN SFR
A Data Stream Command will generate an interrupt
to the internal CPU prior to being read and after
completion of the previous operation The DSC can
then be read via the COMMAND IN SFR Data can
only be read via the FIFO IN SFR and Data Stream
Commands via the COMMAND IN SFR Attempting
to read Data Stream Commands as data by address-
ing the FIFO IN SFR will result in ‘‘0FFH’’ being
read and the Input FIFO Read Pointer will remain
intact (This prevents accidental misreading of Data
Stream Commands ) Attempting to read data as
Data Stream Commands will have the same conse-
quence
The Input FIFO Channel addressing is controlled by
the Input FIFO Read and Write Pointer SFRs These
SFRs are read only registers during normal opera-
tion However during FIFO DMA Freeze Mode (See
FIFO-External Host Interface FIFO DMA Freeze
Mode description) the internal CPU has write ac-
cess to them Any write to these registers in normal
mode will have no effect The Input Write Pointer
SFR contains the address location to which data
commands are written from the Input Buffer Latch
The write pointer is automatically incremented after
each write and is reset to zero if equal to the CBP
as the Input FIFO operates as a circular buffer
If a write is performed on an empty FIFO the first
byte is also written into the FIFO IN or COMMAND
IN SFR If the Host continues writing while the Input
FIFO is full an external interrupt if enabled is sent
to the host to signal the overrun condition The
writes are ignored by the FIFO control logic Similar-
ly an internal CPU read of an empty FIFO will cause
an underrun error interrupt to be generated to the
internal CPU and a value of ‘‘0FFH’’ will be read by
the internal CPU
The Read Pointer SFR holds the address of the next
byte to be read from the Input FIFO An Input FIFO
read operation post-increments the Input Read
Pointer SFR and loads a new data byte into the
FIFO IN SFR or a Data Stream Command into the
COMMAND IN SFR at the end of the read cycle
An Input FIFO Request for Service (via DMA Inter-
rupt or a flag) is generated to the Host whenever
more data can be written into the Input FIFO For
efficient utilization of the Host a ‘‘threshold’’ value
can be programmed into the Input FIFO Threshold
SFR The range of values of the Input FIFO Thresh-
old SFR can be from 0 to (CBP-3) The Request for
Service Interrupt is generated only after the Input
FIFO has room to accommodate a threshold number
of bytes or more The threshold is equal to the total
number of bytes assigned to the Input FIFO (CBP)
minus the number of bytes programmed in the Input
FIFO Threshold SFR With this feature the Host is
assured that it can write at least a threshold number
of bytes to the Input FIFO channel without worrying
about an overrun condition Once the Request for
Service is generated it remains active until the Input
FIFO becomes full
Output FIFO Channel
The Output FIFO Channel provides data transfer
from the UPI-452 internal CPU to the external Host
(Figure 6)
The registers associated with the Output Channel
during normal operation are listed in Table 2
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