UPI-452 Datasheet, PDF(46/53 Page) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

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UPI-452 Datasheet, PDF (46/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

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UPI-452

D C CHARACTERISTICS TA e 0 C to 70 C VCC e 5V g10% VSS e 0V (Continued)

Symbol

Parameter

Min Max Units

Test Conditions

ILI

Input Leakage Current

(except Ports 1 2 3 4)

g10

0 45V k VIN k VCC

IOZ

Output Leakage Current

(except Ports 1 2 3 4)

g10

0 45V k VOUT k VCC

ICC

ICCI

IPD

RRST

Operating Current

Idle Mode Current

Power Down Current

100

Reset Pulldown Resistor 50

150

VCC e 5 5V 14 MHz (Note 4)

VCC e 5 5V 14 MHz (Note 5)

VCC e 2V (Note 3)

CIO

Pin Capacitance

1 MHz TA e 25 C

(sampled not tested on all parts)

NOTES

1 Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLS of ALE and Ports

1 and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1-

to-0 transitions during bus operations In the worst cases (capacitive loading l 100 pF) the noise pulse on the ALE line may

exceed 0 8V In such cases it may be desirable to qualify ALE with a Schmitt Trigger or use an address latch with a Schmitt

Trigger STROBE input

2 Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall before the 0 9 VCC

specification when the address bits are stabilizing

3 Power DOWN ICC is measured with all output pins disconnected EA e Port 0 e VCC XTAL2 N C RST e VSS DB e

VCC WR e RD e DACK e CS e A0 e A1 e A2 e VCC Power Down Mode is not supported on the 87C452P

4 ICC is measured with all output pins disconnected XTAL1 driven with TCLCH TCHCL e 5 ns VIL e VSS a 0 5V VIH e

VCC b 0 5V XTAL2 N C EA e RST e Port 0 e VCC WR e RD e DACK e CS e A0 e A1 e A2 e VCC ICC would be

slightly higher if a crystal oscillator is used

5 Idle ICC is measured with all output pins disconnected XTAL1 driven with TCLCH TCHCL e 5 ns VIL e VSS a 0 5V

VIH e VCC b 0 5V XTAL2 N C Port 0 e VCC EA e RST e VSS WR e RD e DACK e CS e A0 e A1 e A2 e VCC

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has 5 characters The first char-

acter is always a âTâ (stands for time) The other

characters depending on their positions stand for

the name of a signal or the logical status of that

signal The following is a list of all the characters and

what they stand for

A Address

C Clock

D Input data

H Logic level HIGH

I Instruction (program memory contents)

L Logic level LOW or ALE

P PSEN

Q Output data

R READ signal

T Time

V Valid

W WRITE signal

X No longer a valid logic level

Z Float

EXAMPLE

TAVLL e Time for Address Valid to ALE Low

TLLPL e Time for ALE Low to PSEN Low

▷