UPI-452 Datasheet, PDF (15/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Figure 6 Output FIFO Channel Functional Block Diagram
231428 – 10
Table 2 Output FIFO Channel Registers
Register Name
Description
1)
Output Buffer Latch
Host CPU Read only
2)
FIFO OUT SFR
Internal CPU Read and Write
3)
COMMAND OUT SFR
Internal CPU Read and Write
4)
Output FIFO Read Pointer SFR
Internal CPU Read only
5)
Output FIFO Write Pointer SFR
Internal CPU Read only
6)
Output FIFO Threshold SFR
Internal CPU Read only
See ‘‘FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE’’ section for FIFO DMA Freeze Mode register characteristics description
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