UPI-452 Datasheet, PDF (4/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
TABLE OF CONTENTS
CONTENTS
Introduction
Table of Contents
List of Tables and Figures
Pin Description
Architectural Overview
Introduction
FIFO Buffer Interface
FIFO Programmable Features
Immediate Commands
DMA
FIFO Slave Interface Functional Description
Overview
Input FIFO Channel
Output FIFO Channel
Immediate Commands
Host Slave Interface Special Function Registers
Slave Interface Special Function Registers
External Host Interface Special Function Registers
FIFO Module External Host Interface
Overview
Slave Interface Address Decoding
Interrupts to the Host
DMA Requests to the Host
FIFO Module Internal CPU Interface
Overview
Internal CPU Access to FIFO via Software Instructions
General Purpose DMA Channels
Overview
Architecture
DMA Special Function Registers
DMA Transfer Modes
External Memory DMA
Latency
DMA Interrupt Vectors
Interrupts When DMA is Active
DMA Arbitration
Interrupts
Overview
FIFO Module Interrupts to Internal CPU
Interrupt Enabling and Priority
FIFO External Host Interface FIFO DMA Freeze Mode
Overview
Initialization
Invoking FIFO DMA Freeze Mode During Normal Operation
FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode
Internal CPU Read Write of the FIFO During FIFO DMA Freeze Mode
Memory Organization
Accessing External Memory
Miscellaneous Special Function Register Descriptions
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