UPI-452 Datasheet, PDF (40/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
HST5 Data Stream Command at Output FIFO
This bit is forced to a ‘‘1’’ during FIFO DMA
Freeze Mode to prevent the external host
CPU from trying to read the DSC Once nor-
mal operation is resumed HST5 will reflect
the Data Command status of the current byte
in the Output FIFO
Shadow Latch (read by the internal CPU)
1 ^e No Data Stream Command (DSC)
0 ^e Data Stream Command at Output FIFO
HST4 Output FIFO Service Request Status
When FIFO DMA Freeze Mode is invoked
this bit no longer reflects the Output FIFO Re-
quest Service Status This bit wll be forced to
a ‘‘1’’
HST3 Input FIFO Error Condition Flag
1 ^e No error
0 ^e One of the following operations has
been attempted by the external host and
is invalid
1) Write into the Input FIFO
2) Write into the Host Control SFR
3) Write into the Immediate Command In
SFR
NOTE
The normal Input FIFO overrun condition is dis-
abled
HST2 Immediate Command In SFR Status
This bit is normally cleared when the internal
CPU reads the IMIN SFR and set when the
external host CPU writes into the IMIN SFR
When the host-slave interface is frozen read-
ing and writing of the IMIN by the internal
CPU will change the shadow latch of this bit
This bit will be read as a ‘‘1’’ by the external
Host
Shadow latch
1 ^e Internal CPU writes into IMIN SFR
0 ^e Internal CPU reads the IMIN SFR
HST1 FIFO DMA Freeze Mode Status
1 ^e FIFO DMA Freeze Mode
0 ^e Normal Operation (non-FIFO DMA
Freeze Mode)
NOTE
This bit is used to indicate to the external Host that
the host-slave interface has been frozen and hence
the external Host functions are now reduced as
shown in Table 8
HST0 Input FIFO Request Service Satus
When slave interface is frozen this bit no
longer reflects the Input FIFO Request Serv-
ice Status This bit will be forced to a ‘‘1’’
40
Slave Status SFR (SSTAT)
The Slave Status SFR is a read-only SFR However
once the slave interface is frozen most of the bits of
this SFR can be changed by the internal CPU by
reconfiguring the FIFO and accessing the FIFO Spe-
cial Function Registers
SST7 Output FIFO Overrun Error Flag
Inoperative in FIFO DMA Freeze Mode
SST6 Immediate Command Out SFR Status
In FIFO DMA Freeze Mode this bit will be
cleared when the internal CPU reads the Im-
mediate Command Out SFR and set when
the internal CPU writes to the Immediate
Command Out Register
SST5 FIFO-External Interface FIFO DMA Freeze
Mode Status
This bit indicates to the internal CPU that
FIFO DMA Freeze Mode is in progress and
that it has write access to the FIFO Control
Host control and Immediate Command SFRs
SST4 Output FIFO Request Service Status
During normal operation this bit indicates to
the internal CPU that the Output FIFO is
ready for more data The status of this bit re-
flects the position of the Output FIFO read
and write pointers Hence in FIFO DMA
Freeze Mode this flag can be changed by the
internal CPU indirectly as the read and write
pointers change
SST3 Input FIFO Underrun Flag
Inoperative during FIFO DMA Freeze Mode
During normal operation a read operation
clears (^e0) this bit when there are no data
bytes in the Input FIFO and deactivated (^e1)
when the Slave Status SFR is read In FIFO
DMA Freeze Mode this bit will not be cleared
by an Input FIFO read underrun error condi-
tion nor will it be reset by the reading of the
Slave Status SFR
SST2 Immediate Command In SFR Status
This bit is normally activated (^e0) when the
external host CPU writes into the Immediate
Command In SFR and deactivated (^e1)
when it is read by the internal CPU In FIFO
DMA Freeze Mode this bit will not be activat-
ed (^e0) by the external Host’s writing of the
Immediate Command IN SFR since this func-
tion is disabled However this bit will be
cleared (^e0) if the internal CPU writes to the
Immediate Command In SFR and it will be set
e_{1) if it reads from the register}