UPI-452 Datasheet, PDF (41/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
SST1 Data Stream Command at Input FIFO Flag
In FIFO DMA Freeze Mode this bit operates
normally It indicates whether the next byte of
data from the Input FIFO is a DSC or data
byte If it is a DSC byte reading from the
FIFO IN SFR will result in reading invalid data
(FFH) and vice versa In FIFO DMA Freeze
Mode this bit still reflects the type of data
byte available from the Input FIFO
SST0 Input FIFO Service Request Flag
During normal operation this bit is activated
(^e0) when the Input FIFO contains bytes that
can be read by the internal CPU and deacti-
vated (^e1) when the Input FIFO does not
need any service from the internal CPU In
FIFO DMA Freeze Mode the status of this bit
should not change unless the pointers of the
Input FIFO are changed In this mode the in-
ternal CPU can indirectly change this bit by
changing the read and write pointers of the
Input FIFO but cannot change it directly
Immediate Command In Out SFR
(IMIN IMOUT)
If FIFO DMA Freeze Mode is in progress writing to
the Immediate Command In SFR by the external
host will be disabled and any such attempt will
cause HST3 to be cleared (^e0) Similarly the Imme-
diate Command Out SFR read operation (by the
host) will be disabled internally and read attempts
will cause HST7 to be cleared (^e0)
Internal CPU Read and Write of the
FIFO During FIFO DMA Freeze Mode
In normal operation the Input FIFO can only be read
by the internal CPU and similarly the Output FIFO
can only be written by the internal CPU During FIFO
DMA Freeze Mode the internal CPU can read the
entire contents of the Input FIFO by programming
the CBP SFR to 7FH setting the IRPR SFR to zero
and then the IWPR SFR to zero Programming the
pointer registers in this order generates a FIFO full
signal to the FIFO logic and enables internal CPU
read operations If the IWPR and IRPR are already
zero the write pointer should be changed to a non-
zero value to clear the empty status then the point-
ers can be set to zero Writing to the IRDR SFR
automatically updates the look ahead registers
In a similar manner the internal CPU can write to all
128 bytes of the FIFO by setting the CBP SFR to
zero setting OWPR SFR to zero and then setting
ORPR SFR to zero This generates a FIFO empty
signal and allows internal CPU write operations to all
128 bytes of the FIFO The Threshold registers also
need to be adjusted when the pointers are changed
(See ‘‘Input and Output FIFO Threshold SFR’’ sec-
tion below )
MEMORY ORGANIZATION
The UPI-452 has separate address spaces for Pro-
gram Memory and Data Memory like the 80C51 The
Program Memory can be up to 64K bytes The lower
8K of Program Memory may reside on-chip The
Data Memory consists of 256 bytes of on-chip RAM
up to 64K bytes of off-chip RAM and a number of
‘‘SFRs’’ (Special Function Registers) which appear
as yet another set of unique memory addresses
Table 11a Internal Memory Addressing
Memory Space
Addressing Method
Lower 128 Bytes of
Internal RAM
Direct or Indirect
Upper 128 Bytes
of Internal RAM
Indirect Only
UPI-452 SFR’s
Direct Only
The 80C51 Special Function Registers are listed in
Table 11a and the additional UPI-452 SFRs are list-
ed in Table 11b A brief description of the 80C51
core SFRs is also provided below
Accessing External Memory
As in the 80C51 accesses to external memory are
of two types Accesses to external Program Memory
and accesses to external Data Memory
External Program Memory is accessed under two
conditions
1) Whenever signal EA ^e 0 or
2) Whenever the program counter (PC) contains a
number that is larger than 1FFFH
This requires that the ROMless versions have EA
wired low to enable the lower 8K program bytes to
be fetched from external memory
External Data Memory is accessed using either the
MOVX DPTR (16 bit address) or the MOVX Ri (8
bit address) instructions or during external data
memory transfers
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