UPI-452 Datasheet, PDF (16/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
The UPI-452 internal CPU transfers data to the Out-
put FIFO via the FIFO OUT SFR and commands via
the COMMAND OUT SFR If the byte is written to
the COMMAND OUT SFR the ninth bit is automati-
cally set (^e1) to indicate a Data Stream Command
If the byte is written to the FIFO OUT SFR the ninth
bit is cleared (^e0) Thus the FIFO OUT and COM-
MAND OUT SFRs are the same but the address de-
termines whether the byte entered in the FIFO is a
DSC or data byte
The Output FIFO preloads a byte into the Output
Buffer Latch When the Host issues a RD signal
the data is immediately read from the Output Buffer
Latch The next data byte is then loaded into the
Output Buffer Latch a flag is set and an interrupt if
enabled is generated if the byte is a DSC (ninth bit
is set) The operation is carefully timed such that an
interrupt can be generated in time for it to be recog-
nized by the Host before its next read instruction
Internal CPU write and external Host read opera-
tions are interleaved at the FIFO so that they appear
to be occurring concurrently
The Output FIFO read and write pointer operation is
the same as for the Input Channel Writing to the
FIFO OUT or COMMAND OUT SFRs will increment
the Output Write Pointer SFR but reading from it will
leave the write pointer unchanged A rollover of the
Output FIFO Write Pointer causes the pointer to be
reset to the value in the Channel Boundary Pointer
(CBP) SFR
If the external host attempts to read a Data Stream
Command as a data byte it will result in invalid data
(0FFH) being read The DSC is not lost because the
invalid read does not increment the pointer Similarly
attempting to read a data byte as a Data Stream
Command has the same result
A Request for Service is generated to the external
Host under the following two conditions
1 ) Whenever the internal CPU has written a thresh-
old number of bytes or more into the Output FIFO
(threshold ^e (OTHR) ^a 1) The threshold num-
ber should be chosen such that the bus latency
time for the external Host does not result in a
FIFO overrun error condition on the internal CPU
side The threshold limit should be large enough
to make a bus request by the UPI-452 to the ex-
ternal host CPU worthwhile Once a request for
service is generated the request remains active
until the Output FIFO becomes empty The range
of values of the FIFO Output Threshold (OTHR)
SFR is from 2 to (80H-CBP)-1 The threshold
number can be programmed via the OTHR SFR
2 ) The second type of Request for Service is called
‘‘Flush Mode’’ and occurs when the internal CPU
writes a Data Stream Command into the Output
FIFO Its purpose is to ensure that a data block
entered into the Output FIFO which is less than
the programmed threshold will generate a Re-
quest for Service interrupt if enabled and be
read or ‘‘Flushed’’ from the Output FIFO by the
external host CPU regardless of the status of the
OTHR SFR
NOTE
The host port read or write strobe (TPW) should be
limited to a maximum of 4 TCLCL This guideline
will eliminate a potential output FIFO Request lock-
up from occurring if the host reads the last byte
from the output FIFO while the UPI-452 is begin-
ning to write another byte to the output FIFO
Immediate Commands
Immediate Commands provide direct communica-
tion between the external Host and UPI-452 Unlike
Data Stream Commands which are entered into the
FIFO the Immediate Command is available to the
receiving CPU directly bypassing the FIFO The Im-
mediate Command can serve as a program vector
pointing into a jump table in the recipients software
Immediate Command Interrupts are generated if en-
abled and a bit in the appropriate Status Register is
set when an Immediate Command is input or output
A similar bit is provided to acknowledge when an
Immediate Command has been read and whether
the register is available to receive another com-
mand The bits are reset when the Immediate Com-
mands are read Two Special Function Registers are
dedicated to the Immediate Command interface Ex-
ternal addressing determines whether the Host is
accessing the Input FIFO or the Immediate Com-
mand IN (IMIN) SFR The internal CPU writes Imme-
diate Commands to the Immediate Command OUT
(IMOUT) SFR
Both processors have the ability to enable or disable
Immediate Command Interrupts By disabling the in-
terrupt the recipient of the Immediate Command
can poll the status SFR and read the Immediate
Command at its convenience Immediate Com-
mands should only be written when the appropriate
Immediate Command SFR is empty (as indicated in
the appropriate status SFR HSTAT SSTAT) Simi-
larly the Immediate Command SFR should only be
read when there is data in the Register
The flowcharts in Figure 7a and 7b illustrate the
proper handshake mechanisms between the exter-
nal Host and internal CPU when handling Immediate
Commands
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