UPI-452 Datasheet, PDF (43/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Miscellaneous Special Function
Register Description
80C51 SFRs
ACCUMULATOR
ACC is the Accumuator SFR The mnemonics for
accumulator-specific instructions however refer to
the accumulator simply as A
B REGISTER
The B SFR is used during multiply and divide opera-
tions For other instructions it can be treated as an-
other scratch pad register
PROGRAM STATUS WORD
The PSW SFR contains program status information
as detailed in Table 12
STACK POINTER
The Stack Pointer register is 8 bits wide It is incre-
mented before data is stored during PUSH and
CALL executions While the stack may reside any-
where in on-chip RAM the Stack Pointer is initialized
to 07H after a reset This causes the stack to begin
at location 08H
DATA POINTER
The Data Pointer (DPTR) consists of a high byte
(DPH) and a low byte (DPL) Its intended function is
to hold a 16-bit address It may be manipulated as a
16-bit register or as two independent 8-bit registers
PORTS 0 TO 4
P0 P1 P2 P3 and P4 are the SFR latches of Ports
0 1 2 3 and 4 respectively
SERIAL DATA BUFFER
The Serial Data Buffer is actually two separate regis-
ters a transmit buffer and a receive buffer register
When data is moved to SBUF it goes to the transmit
buffer where it is held for serial transmission (Mov-
ing a byte to SBUF is what initiates the transmis-
sion ) When data is moved from SBUF it comes
from the receive buffer
TIMER COUNTER SFR
Register pairs (TH0 TL0) and (TH1 TL1) are the
16-bit counting registers for Timer Counters 0 and 2
POWER CONTROL SFR (PCON)
The PCON Register (Table 13) controls the power
down and idle modes in the UPI-452 as well as pro-
viding the ability to double the Serial Channel baud
rate There are also two general purpose flag bits
available to the user Bits 5 and 6 are used to set the
HOLD HOLD Acknowledge mode (see ‘‘General
Purpose DMA Channels’’ section) and bit 4 is not
used
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