UPI-452 Datasheet, PDF (32/53 Pages) Intel Corporation – CHMOS PROGRAMMABLE I/O PROCESSOR

UPI-452
Figure 11 DMA Transfer from Internal Memory to Internal Memory
231428 – 16
INTERNAL INTERRUPTS
Overview
The UPI-452 provides a total of eight interrupt sourc-
es (Table 6) Their operation is the same as in the
80C51 with the addition of three new interrupt
sources for the UPI-452 FIFO and DMA features
These added interrupts have their enable and priori-
ty bits in the Interrupt Enable and Priority (IEP) SFR
The IEP SFR is in addition to the 80C51 Interrupt
Enable (IE) and Interrupt Priority (IP) SFRs The add-
ed interrupt sources are also globally enabled or dis-
abled by the EA bit in the Interrupt Enable SFR Ta-
ble 6 lists the eight interrupt sources in order of pri-
ority Table 7 lists the eight interrupt sources and
their respective address vector location in program
memory (DMA interrupts are discussed in the ‘‘Gen-
eral Purpose DMA Channels’’ section Additional in-
terrupt information for Timer Counter Serial Chan-
nel External Interrupt may be found in the Microcon-
troller Handbook for the 80C51 )
FIFO Module Interrupts to Internal CPU
The FIFO module generates interrupts to the inter-
nal CPU whenever the FIFO requests service or
when a Data Stream Command is in the COMMAND
IN SFR The Input FIFO will request service whenev-
er it becomes full or not empty depending on bit 1 of
the Slave Control SFR (IFRS) Similarly the Output
Table 6 Interrupt Priority
Interrupt Source
Priority Level
(highest)
External Interrupt 0
0
Internal Timer Counter 0
1
DMA Channel 0 Request
2
External Interrupt 1
3
DMA Channel 1 Request
4
Internal Timer Counter 1
5
FIFO - Slave Bus Interface
6
Serial Channel
7
(lowest)
Table 7 Interrupt Vector Addresses
Interrupt Source
Starting Address
External Interrupt 0
3 (003H)
Internal Timer Counter 0
11 (00BH)
External Interrupt 1
19 (013H)
Internal Timer Counter 1
27 (01BH)
Serial Channel
35 (023H)
FIFO - Slave Bus Interface
43 (02BH)
DMA Channel 0 Request
51 (033H)
DMA Channel 1 Request
59 (03BH)
FIFO requests service when it becomes empty or
not full as determined by bit 0 of the Slave Control
SFR (OFRS) Request for Service interrupts are
generated only if enabled by the internal CPU via the
Interrupt Enable SFR and the Slave Control Regis-
ter
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