GS2971A Datasheet, PDF (98/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-26:GSPI Timing Parameters (50% levels; 3.3V or 1.8V operation)
Parameter
CS low before SCLK rising edge
SCLK period
SCLK duty cycle
Input data setup time
Time between end of Command Word (or data in
Auto-Increment mode) and the first SCLK of the
following Data Word – write cycle
Time between end of Command Word (or data in
Auto-Increment mode) and the first SCLK of the
following Data Word – read cycle.
Time between end of Command Word (or data in
Auto-Increment mode) and the first SCLK of the
following Data Word – read cycle - ANC FIFO Read
Output hold time (15pF load)
CS high after last SCLK rising edge
Input data hold time
* when the device is locked to these data rates
Symbol
Min
t₀
1.5
t₁
16.67
t₂
40
t₃
1.5
t₄
PCLK (MHz)
ns
unlocked
100
27.0
37.1
74.25
13.5
148.5
6.7
t₅
PCLK (MHz)
ns
unlocked
27.0
148.4*
74.25
53.9*
148.5
27*
t₅
222.6
t₆
1.5
t₇
PCLK (MHz)
ns
unlocked
445
27.0
37.1
74.25
13.5
148.5
6.7
t₈
1.5
This timing must be satisfied across all ambient temperature and power supply
operating conditions, as described in the Electrical Characteristics on page 17.
Typ
Max Units
−
−
ns
−
−
ns
50
60
%
−
−
ns
−
−
ns
−
−
ns
−
−
ns
−
−
ns
−
−
ns
−
−
ns
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
98 of 152