GS2971A Datasheet, PDF (115/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
401h
DBN_ERR
SAMP_DBNB_ERR
SAMP_DBNA_ERR
402h
CTRB_DET
CTRA_DET
ACS_DET3_4B
ACS_DET1_2B
ACS_DET3_4A
ACS_DET1_2A
REGEN
RSVD
ACS_APPLY
ACS_REGEN
Bit
7
6
5
4
3
2
1
0
15-2
1
0
Description
Set when Secondary group data
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
Set when Primary group data
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
Set when Secondary group audio
control packet is detected. Write
‘1’ to clear.
Set when Primary group audio
control packet is detected. Write
‘1’ to clear.
Secondary group audio status
detected for channels 3 and 4.
Write ‘1’ to clear.
Secondary group audio status
detected for channels 1 and 2.
Write ‘1’ to clear.
Primary group audio status
detected for channels 3 and 4.
Write ‘1’ to clear.
Primary group audio status
detected for channels 1 and 2.
Write ‘1’ to clear.
Reserved.
Cause channel status data in
ACSR[183:0] to be transferred to
the channel status replacement
mechanism. The transfer does not
occur until the next status
boundary.
Specifies that Audio Channel
Status of all channels should be
replaced with ACSR[183:0] field.
0: Do not replace Channel Status
1: Replace Channel Status of all
channels
R/W Default
ROCW
0
ROCW
0
ROCW
0
ROCW
0
ROCW
0
ROCW
0
ROCW
0
ROCW
0
R/W
0
R/W
0
R/W
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
115 of 152