GS2971A Datasheet, PDF (111/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-27:Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
037h
ERROR_MASK_1
RSVD
ERROR_MASK_1
038h
ERROR_MASK_2
RSVD
ERROR_MASK_2
039h
ACGEN_CTRL
RSVD
SCLK_INV
AMCLK_INV
RSVD
AMCLK_SEL
03Ah
-6Bh
06Ch
RSVD
CLK_GEN
RSVD
RSVD
DEL_LINE_CLK_SEL
DEL_LINE_OFFSET
Bit Description
15-11
10-0
15-7
6-0
15-5
4
3
2
1-0
15-0
Reserved.
Error mask for global error vector
(3G Level B Data Stream 1, 3G Level
A, HD, SD):
bit[0]: EAV_ERR_DS1 mask
bit[1]: SAV_ERR_DS1 mask
bit[2]: LNUM_ERR_DS1 mask
bit[3]: YCRC_ERR_DS1 mask
bit[4]: CCRC_ERR_DS1 mask
bit[5]: YCS_ERR_DS1 mask
bit[6]: CCS_ERR_DS1 mask
bit[7]: Reserved
bit[8]: AP_CRC_ERR mask
bit[9]: FF_CRC_ERR mask
bit[10]: VD_STD_ERR_DS1 mask
Reserved.
Error mask for global error vector
(3G Level B Data Stream 2 only):
bit[0]: EAV_ERR_DS2 mask
bit[1]: SAV_ERR_DS2 mask
bit[2]: LNUM_ERR_DS2 mask
bit[3]: YCRC_ERR_DS2 mask
bit[4]: CCRC_ERR_DS2 mask
bit[5]: YCS_ERR_DS2 mask
bit[6]: CCS_ERR_DS2 mask
Reserved.
Invert polarity of output serial
audio clock.
Invert polarity of output audio
master clock.
Reserved.
Audio Master Clock Select.
0: 128 fs
1: 256 fs
2: 512 fs
Reserved.
15-6
5
4-0
Reserved.
Choses between the in-phase (0)
and quadrature (1) clocks for DDR
mode.
Controls the offset for the delay
line.
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
111 of 152