GS2971A Datasheet, PDF (127/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
480h
ACSR_BYTE_0 ACSR_BYTE0
481h
482h
483h
484h
485h
486h
487h
488h
489h
48Ah
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
ACSR_BYTE_1
ACSR_BYTE_2
ACSR_BYTE_3
ACSR_BYTE_4
ACSR_BYTE_5
ACSR_BYTE_6
ACSR_BYTE_7
ACSR_BYTE_8
ACSR_BYTE_9
ACSR_BYTE_10
ACSR_BYTE_11
ACSR_BYTE_12
ACSR_BYTE_13
ACSR_BYTE_14
ACSR_BYTE_15
ACSR_BYTE_16
ACSR_BYTE_17
ACSR_BYTE_18
ACSR_BYTE_19
ACSR_BYTE_20
ACSR_BYTE_21
ACSR_BYTE_22
ACSR_BYTE1
ACSR_BYTE2
ACSR_BYTE3
ACSR_BYTE4
ACSR_BYTE5
ACSR_BYTE6
ACSR_BYTE7
ACSR_BYTE8
ACSR_BYTE9
ACSR_BYTE10
ACSR_BYTE11
ACSR_BYTE12
ACSR_BYTE13
ACSR_BYTE14
ACSR_BYTE15
ACSR_BYTE16
ACSR_BYTE17
ACSR_BYTE18
ACSR_BYTE19
ACSR_BYTE20
ACSR_BYTE21
ACSR_BYTE22
Bit Description
7-0 Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register for 23 registers.
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
7-0 −
R/W
R
Default
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
R/W
0
R/W
0
R/W
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
127 of 152