GS2971A Datasheet, PDF (112/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-27:Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
06Dh
IO_DRIVE
_STRENGTH
RSVD
IO_DS_CTRL_DOUT_MSB
IO_DS_CTRL_STAT
IO_DS_CTRL_DOUT_LSB
06Eh
- 072h
073h
074h
-084h
085h
RSVD
RSVD
EQ_BYPASS
RSVD
EQ_BYPASS
RSVD
RSVD
RSVD
RSVD
LOCK_NOISE
_IMM_INCR
RSVD
LOCK_NOISE_IMM_INCR
RSVD
RSVD
Bit
15-6
5-4
3-2
1-0
−
Description
Reserved.
Drive strength adjustment for
DOUT[19:10] outputs and PCLK
output:
00: 4mA;
01: 8mA;
10: 10mA(1.8V), 12mA(3.3V);
11: 12mA(1.8V), 16mA(3.3V)
Drive strength adjustment for
STAT[5:0] outputs:
00: 4mA;
01: 6mA;
10: 8mA(1.8V), 10mA(3.3V);
11: 10mA(1.8V), 12mA(3.3V)
Drive strength adjustment for
DOUT[9:0] outputs:
00: 4mA;
01: 6mA;
10: 8mA(1.8V), 10mA(3.3V);
11: 10mA(1.8V), 12mA(3.3V)
Reserved.
15-10
9
8-0
15-0
Reserved.
0: non-bypass EQ
1: bypass EQ
Reserved.
Reserved.
15-11
10
9-0
Reserved.
Enables extra noise-immunity on
SMPTE detected lock when HIGH
by forcing detection of three TRS
words with the last two TRS words
having the same alignment before
locking to SMPTE. Enable this only
for AUTO/MAN = HIGH.
Reserved.
R/W
R/W
R/W
Default
0
2
R/W
2
R/W
3
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
112 of 152