GS2971A Datasheet, PDF (101/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-27:Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
001h
IOPROC_2
DS_SWAP_3G
LEVEL_B2A_CONV
_DISABLE_MASK
ANC_EXT_SEL_DS2_DS1
AUDIO_SEL_DS2_DS1
RSVD
ILLEGAL_WORD_REMAP
_DS2_MASK
ANC_CHECKSUM
_INSERTION_DS2_MASK
CRC_INS_DS2_MASK
LNUM_INS_DS2_MASK
TRS_INS_DS2_MASK
Bit Description
9
Swaps Data Stream 1 (DS1) and
Data Stream 2 (DS2) at the output
in 3G mode.
In 20-bit output mode, DS1 shall be
present on DOUT pins [19:10] and
DS2 shall be present on DOUT pins
[9:0] by default. When
DS_SWAP_3G is set to '1', DS2 shall
be present on DOUT pins [19:10]
and DS1 shall be present on DOUT
pins [9:0]
In 10-bit (DDR) output mode, DS2
shall precede DS1 by default. When
DS_SWAP_3G is set to '1', DS1 shall
precede DS2.
8
Disable conversion of a 3G Level B
input to a 3G Level A format. Only
effective if in 3G Level B mode.
Default is active HIGH (disabled), so
Level B inputs are formatted as
Level B outputs.
7
Selects data stream to extract ANC
data from (valid for 3G Level B
data).
6
Selects data stream to be sent to
audio core (valid for 3G Level B
data).
5
Reserved.
4
Disables illegal word remapping in
Data Stream 2 (3G Level B only).
3
Disables insertion of ancillary data
checksums in Data Stream 2 (3G
Level B only).
2
Disables insertion of CRC words in
Data Stream 2 (3G Level B only).
1
Disables insertion of line numbers
in Data Stream 2 (3G Level B only).
0
Disable insertion of TRS words in
Data Stream 2 (3G Level B only).
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
1
0
0
0
0
0
0
0
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
101 of 152