GS2971A Datasheet, PDF (10/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 1-1:Pin Descriptions (Continued)
Pin
Number
A5, A6, B5,
B6, C5, C6
A7, D10,
G10, K7
A8
Name
STAT[0:5]
IO_VDD
PCLK
Timing
Type
Description
Output
Input Power
Output
MULTI-FUNCTIONAL OUTPUT PORT.
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
Each of the STAT [0:5] pins can be configured individually to output
one of the following signals:
Signal
H/HSYNC
V/VSYNC
F/DE
LOCKED
Y/1ANC
C/2ANC
DATA ERROR
VIDEO ERROR
AUDIO ERROR
EDH DETECTED
CARRIER DETECT
RATE_DET0
RATE_DET1
Default
STAT0
STAT1
STAT2
STAT3
STAT4
−
STAT5
−
−
−
−
−
−
POWER connection for digital I/O. Connect to 3.3V or 1.8V DC
digital.
PARALLEL DATA BUS CLOCK
Please refer to the Output Logic parameters in the DC Electrical
Characteristics table for logic level threshold and compatibility.
3G 10-bit or 20-bit mode
PCLK @ 148.5 or 148.5/1.001MHz
HD 10-bit mode
PCLK @ 148.5 or 148.5/1.001MHz
HD 20-bit mode
PCLK @ 74.25 or 74.25/1.001MHz
SD 10-bit mode
PCLK @ 27MHz
SD 20-bit mode
PCLK @ 13.5MHz
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
10 of 152