GS2971A Datasheet, PDF (143/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-29:HD and 3G Audio Core Configuration and Status Registers (Continued)
Address
295h
Register Name Bit Name
ACSR_BYTE_21
RSVD
ACSR21
296h
ACSR_BYTE_22
RSVD
ACSR22
297h
RSVD
RSVD
Bit Description
15-8
7-0
15-8
7-0
15-0
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
R/W
R/W
W
Default
0
0
R/W
0
W
0
R
29
Table 4-30:ANC Extraction FIFO Access Registers
Address
Register Name
Bit
800h -
BFFh
ANC_PACKET_BANK
15-0
Description
Extracted Ancillary Data 91024 words.
Bit 15-8: Most Significant Word (MSW).
Bit 7-0: Least Significant Word (LSW).
See Section 4.18.8.
Legend:
R = Read only
ROCW = Read Only, Clear on Write
R/W = Read or Write
W = Write only
4.22 JTAG Test Operation
When the JTAG/HOST pin of the GS2971A is set HIGH, the host interface port is
configured for JTAG test operation. In this mode, pins E7, F8, F7, and E8 become TDO,
TCK, TMS, and TDI. In addition, the RESET_TRST pin operates as the test reset pin.
Boundary scan testing using the JTAG interface is enabled in this mode.
There are two ways in which JTAG can be used:
1. As a stand-alone JTAG interface to be used at in-circuit ATE (Automatic Test
Equipment) during PCB assembly.
2. Under control of a host processor for applications such as system power on self
tests.
When the JTAG tests are applied by ATE, care must be taken to disable any other devices
driving the digital I/O pins. If the tests are to be applied only at ATE, this can be
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
R/W
R
Default
0
143 of 152