GS2971A Datasheet, PDF (65/152 Pages) Gennum Corporation – Integrated audio clock generator

4.15.2 EDH Flag Detection
The EDH flags for ancillary data, active picture, and full field regions are extracted from
the detected EDH packets and placed in the EDH_FLAG_IN register.
When the EDH_FLAG_UPDATE_MASK bit in the host interface is set HIGH, the
GS2971A updates the Ancillary Data, Full Field, and Active Picture EDH flags according
to SMPTE RP165. The updated EDH flags are available in the EDH_FLAG_OUT register.
The EDH packet output from the device contains these updated flags.
One set of flags is provided for both fields 1 and 2. The field 1 flag data is overwritten by
the field 2 flag data.
When EDH packets are not detected, the UES flags in the EDH_FLAG_OUT register are
set HIGH to signify that the received signal does not support Error Detection and
Handling. In addition, the EDH_DETECT bit is set LOW. These flags are set regardless of
the setting of the EDH_FLAG_UPDATE_MASK bit.
EDH_FLAG_OUT and EDH_FLAG_IN may be read via the host interface at any time
during the received frame except on the lines defined in SMPTE RP165, when these flags
are updated.
The GS2971A indicates the CRC validity for both active picture and full field CRCs. The
AP_CRC_V bit in the host interface indicates the active picture CRC validity, and the
FF_CRC_V bit indicates the full field CRC validity. When EDH_DETECT = LOW, these
bits are cleared.
The EDH_FLAG_OUT and EDH_FLAG_IN register values remain set until overwritten by
the decoded flags in the next received EDH packet. When an EDH packet is not detected
during vertical blanking, the flag registers are cleared at the end of the vertical blanking
period.
4.16 Video Signal Error Detection & Indication
The GS2971A includes a number of video signal error detection functions. These are
provided to enhance operation of the device when operating in SMPTE mode
(SMPTE_BYPASS = HIGH). These features are not available in the other operating modes
of the device (i.e. when SMPTE_BYPASS = LOW).
Signal errors that can be detected include:
1. TRS errors.
2. HD line based CRC errors.
3. EDH errors.
4. HD line number errors.
5. Video standard errors.
The device maintains an ERROR_STAT_X register. Each error condition has a specific
flag in the ERROR_STAT_X register, which is set HIGH whenever an error condition is
detected.
An ERROR_MASK register is also provided, allowing the user to select which error
conditions are reported. Each bit of the ERROR_MASK register corresponds to a unique
error type.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
65 of 152