GS2971A Datasheet, PDF (118/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
407h
SD_AUDIO_ERR
OR_MASK
RSVD
RSVD
RSVD
RSVD
EN_ACS_DET3_4B
EN_ACS_DET1_2B
EN_ACS_DET3_4A
EN_ACS_DET1_2A
EN_CTRB_DET
EN_CTRA_DET
EN_DBNB_ERR
EN_DBNA_ERR
407h
SD_AUDIO_ERR EN_ADPG4_DET
OR_MASK
EN_ADPG3_DET
EN_ADPG2_DET
EN_ADPG1_DET
Bit Description
15 Reserved.
14 Reserved
13 Reserved
12 Reserved
11 Asserts AUDIO_ERROR when
ACS_DET3_4B (Reg 401 bit 3) flag is
set.
10 Asserts AUDIO_ERROR when
ACS_DET1_2B (Reg 401 bit 2) flag is
set.
9
Asserts AUDIO_ERROR when
ACS_DET3_4A (Reg 401 bit 1) flag
is set.
8
Asserts AUDIO_ERROR when
ACS_DET1_2A (Reg 401 bit 0) flag
is set.
7
Asserts AUDIO_ERROR when
CTRB_DET (Reg 401 bit 5) flag is
set.
6
Asserts AUDIO_ERROR when
CTRA_DET (Reg 401 bit 4) flag is
set.
5
Asserts AUDIO_ERROR when
SAMP_DBNB_ERR (Reg 401 bit 7)
flag is set.
4
Asserts AUDIO_ERROR when
SAMP_DBNA_ERR (Reg 401 bit 6)
flag is set.
3
Asserts AUDIO_ERROR when the
ADPG4_DET (Reg 403 bit 7) flag is
set.
2
Asserts AUDIO_ERROR when the
ADPG3_DET (Reg 403 bit 6) flag is
set.
1
Asserts AUDIO_ERROR when the
ADPG2_DET (Reg 403 bit 5) flag is
set.
0
Asserts AUDIO_ERROR when the
ADPG1_DET (Reg 403 bit 4) flag is
set.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
118 of 152