GS2971A Datasheet, PDF (105/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-27:Video Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
006h
DATA_FORMAT_
DS1
FF_CRC_V
AP_CRC_V
VD_STD_DS1
CDATA_FORMAT_DS1
YDATA_FORMAT_DS1
007h
DATA_FORMAT_
DS2
RSVD
VD_STD_DS2
CDATA_FORMAT_DS2
YDATA_FORMAT_DS2
Bit Description
15
14
13-8
7-4
3-0
15-14
13-8
7-4
3-0
EDH Full Field CRC Validity bit.
EDH Active Picture CRC Validity bit.
Detected Video Standard for 3G
Level B Data Stream 1, 3G Level A,
HD and SD inputs.
Data format as indicated in
Chroma channel for 3G Level B
Data Stream 1, HD and SD inputs;
Data format as indicated in Data
Stream 2 for 3G Level A inputs.
Data format as indicated in Luma
channel for 3G Level B Data Stream
1, HD and SD inputs;
Data format as indicated in Data
Stream 1 for 3G Level A inputs.
Reserved.
Detected Video Standard for Data
Stream 2 (3G Level B only).
Data Format as indicated in
Chroma channel for Data Stream 2
(3G Level B only).
Data Format as indicated in Luma
channel for Data Stream 2 (3G
Level B only).
R/W
R
R
R
R
R
R
R
R
R
Default
0
0
29
15
15
0
29
15
15
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
105 of 152