GS2971A Datasheet, PDF (133/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-29:HD and 3G Audio Core Configuration and Status Registers (Continued)
Address
208h
Register Name Bit Name
CFG_AUD_2
RSVD
SEL_PHASE_SRC
LSB_FIRSTB
LSB_FIRSTA
FORCE_M
FORCE_MEQ1001
IGNORE_PHASE
FORCE_ACLK128
RSVD
RSVD
EN_NO_PHASEB
209h
EN_NO_PHASEA
CFG_AUD_3
RSVD
MISSING_PHASE
NO_PHASEB_DATA
NO_PHASEA_DATA
Bit Description
15-11
10
9
8
7
6
5
4
3
2
1
0
15-3
2
1
0
Reserved.
Selects between the Primary and
Secondary embedded phase info.
Causes the Secondary group serial
output formats to use LSB first.
Causes the Primary group serial
output formats to use LSB first.
Disables M value detection and
forces M value to that specified by
FORCE_MEQ1001.
Specifies M value when FORCE_M is
set.
1: M= 1.001
0: M = 1.000
Causes the Demultiplexer to ignore
the embedded clock info in both
the Primary and Secondary group
audio data packets. Clock is
generated based on the video
format and M value.
Causes the core to ignore
embedded clock info and derive
phase information from ACLK128.
Reserved
Reserved
Asserts AUDIO_ERROR when
NO_PHASEB_DATA (Reg 209 bit 1)
is set.
Asserts AUDIO_ERROR when
NO_PHASEA_DATA (Reg 209 bit 0)
is set.
Reserved.
Embedded phase info for chosen
group missing or incorrect.
Secondary group has invalid
embedded clock information.
Primary group has invalid
embedded clock information.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
133 of 152