GS2971A Datasheet, PDF (91/152 Pages) Gennum Corporation – Integrated audio clock generator

Clear the audio FIFO by asserting CLEAR_AUDIO and de-asserting at least one frame
later. When the FIFOs are in the clear state, audio will be muted but audio clocks will
continue to run.
When switching between 525 and 625 formats, it is recommended that the device be
reset to keep the delays through the audio FIFO the same between channels.
4.19.3.4 Audio Crosspoint Block
The Audio Crosspoint is used for audio output channel re-mapping. This feature allows
any of the selected audio channels in Group A or Group B to be output on any of the eight
output channels. The default setting is for one to one mapping, where AOUT_1/2 is
extracted from Group A CH1 and CH2, AOUT_3/4 is extracted from Group A CH3 and
CH4, and so on.
NOTE: If audio samples from embedded audio packets with the group set in IDA[1:0] are
to be paired with samples from the group set in IDB[1:0], all of the channels must have
been derived from the same Word Clock and must be synchronous.
The output channel is set in the OPn_SRC[2:0] host interface registers. Table 4-22 lists the
3-bit address for audio channel mapping.
Table 4-22:Audio Channel Mapping Codes
Audio Output Channel
1
2
3
4
5
6
7
8
3-bit Host Interface
Source Address
000
001
010
011
100
101
110
111
4.19.3.5 Serial Audio Output Word Length
The audio output, in serial modes, has a selectable 24, 20 or 16-bit sample word length.
The ASWL[1:0] host interface register is used to configure the audio output sample word
length. Figure 4-23 shows the host interface 2-bit code for setting the audio sample word
length. When the presence of extended audio packets is detected in SD modes, the audio
de-embedder defaults to 24-bit audio sample word length.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
91 of 152