GS2971A Datasheet, PDF (145/152 Pages) Gennum Corporation – Integrated audio clock generator

4.23 Device Power-up
Because the GS2971A is designed to operate in a multi-voltage environment, any
power-up sequence is allowed. The charge pump, phase detector, core logic, serial
digital output and I/O buffers can all be powered up in any order.
4.24 Device Reset
NOTE: At power-up, the device must be reset to operate correctly.
In order to initialize all internal operating conditions to their default states, hold the
RESET_TRST signal LOW for a minimum of t_reset = 1ms after all power supplies are stable.
There are no requirements for power supply sequencing.
When held in reset, all device outputs are driven to a high-impedance state.
Nominal Level
95% of Nominal Level
Supply Voltage
RESET_TRST
Figure 4-56:Reset Pulse
treset
Reset
treset
Reset
4.25 Standby Mode
The STANDBY pin reduces power to a minimum by disabling all circuits except for the
register configuration. Upon removal of the signal to the STANDBY pin, the device
returns to its previous operating condition within 1 second, without requiring input
from the host interface.
NOTE: In standby mode or reset, the crystal buffer output remains enabled. This allows
users to reset the GS2971A device without resetting other downstream devices that are
using the same reference. This also allows users to put the GS2971A device in standby
mode and still use the loop-through mode.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
145 of 152