GS2971A Datasheet, PDF (114/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
400h
CFG_AUD
IDB
IDA
401h
DBN_ERR
EXT_DET3_4B
EXT_DET1_2B
EXT_DET3_4A
EXT_DET1_2A
CTL_DBNB_ERR
CTL_DBNA_ERR
EXT_DBNB_ERR
EXT_DBNA_ERR
Bit Description
R/W Default
3-2 Specifies the Secondary audio
R/W
1
group to extract.
00: Audio group #1
01: Audio group #2
10: Audio group #3
11: Audio group #4
NOTE: Should IDA and IDB be set
to the same value, they
automatically revert to their
default values.
1-0 Specifies the Primary audio group
R/W
0
to extract.
00: Audio group #1
01: Audio group #2
10: Audio group #3
11: Audio group #4
NOTE: Should IDA and IDB be set
to the same value, they
automatically revert to their
default values.
15 Set when Secondary group
ROCW
0
channels 3 and 4 have extended
data. Write ‘1’ to clear.
14 Set when Secondary group
ROCW
0
channels 1 and 2 have extended
data. Write’1’ to clear.
13 Set when Primary group channels 3 ROCW
0
and 4 have extended data. Write
‘1’ to clear.
12 Set when Primary group channels 1 ROCW
0
and 2 have extended data. Write
‘1’ to clear.
11 Set when Secondary group control ROCW
0
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
10 Set when Primary group control
ROCW
0
packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
9
Set when Secondary group
ROCW
0
extended data packet Data Block
Number sequence is discontinuous.
Write ‘1’ to clear.
8
Set when Primary group extended ROCW
0
data packet Data Block Number
sequence is discontinuous. Write
‘1’ to clear.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
114 of 152