GS2971A Datasheet, PDF (121/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
424h
PRIM_AUD_
DELAY_1
RSVD
DEL1A_1
EBIT1A
425h
PRIM_AUD_
DELAY_2
RSVD
DEL1A_2
426h
PRIM_AUD_
DELAY_3
RSVD
DEL1A_3
427h
PRIM_AUD_
DELAY_4
RSVD
DEL2A_4
EBIT2A
428h
PRIM_AUD_
DELAY_5
RSVD
DEL2A_5
429h
PRIM_AUD_
DELAY_6
RSVD
DEL2A_6
42Ah
PRIM_AUD_
DELAY_7
RSVD
DEL3A_7
EBIT3A
42Bh
PRIM_AUD_
DELAY_8
RSVD
DEL3A_8
42Ch
PRIM_AUD_
DELAY_9
RSVD
DEL3A_9
42Dh
PRIM_AUD_
DELAY_10
RSVD
DEL4A_10
EBIT4A
Bit
15-9
8-1
0
15-9
8-0
15-9
8-0
15-9
8-1
0
15-9
8-0
15-9
8-0
15-9
8-1
0
15-9
8-0
15-9
8-0
15-9
8-1
0
Description
Reserved.
Primary Audio group delay data
for channel 1.
Primary Audio group delay data
valid flag for channel 1.
Reserved.
Primary Audio group delay data
for channel 1.
Reserved.
Primary Audio group delay data
for channel 1.
Reserved.
Primary Audio group delay data
for channel 2.
Primary Audio group delay data
valid flag for channel 2.
Reserved.
Primary Audio group delay data
for channel 2.
Reserved.
Primary Audio group delay data
for channel 2.
Reserved.
Primary Audio group delay data
for channel 3.
Primary Audio group delay data
valid flag for channel 3.
Reserved.
Primary Audio group delay data
for channel 3.
Reserved.
Primary Audio group delay data
for channel 3.
Reserved.
Primary Audio group delay data
for channel 4.
Primary Audio group delay data
valid flag for channel 4.
R/W
R/W
R
Default
0
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
R
0
R/W
0
R
0
R/W
0
R
0
R/W
0
R
0
R
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
121 of 152