GS2971A Datasheet, PDF (4/152 Pages) Gennum Corporation – Integrated audio clock generator

Contents
Key Features ........................................................................................................................................................1
Applications ......................................................................................................................................................... 1
Description ........................................................................................................................................................... 2
Functional Block Diagram ..............................................................................................................................3
1. Pin Out...............................................................................................................................................................9
1.1 Pin Assignment ..................................................................................................................................9
1.2 Pin Descriptions ................................................................................................................................9
2. Electrical Characteristics ......................................................................................................................... 17
2.1 Absolute Maximum Ratings ....................................................................................................... 17
2.2 Recommended Operating Conditions .................................................................................... 17
2.3 DC Electrical Characteristics ..................................................................................................... 18
2.4 AC Electrical Characteristics ..................................................................................................... 20
3. Input/Output Circuits ............................................................................................................................... 26
4. Detailed Description.................................................................................................................................. 29
4.1 Functional Overview .................................................................................................................... 29
4.2 SMPTE 425M Mapping - 3G Level A and Level B Formats ............................................... 30
4.2.1 Level A Mapping................................................................................................................ 30
4.2.2 Level B Mapping ................................................................................................................ 30
4.3 Serial Digital Input ........................................................................................................................ 31
4.3.1 Integrated Adaptive Cable Equalizer.......................................................................... 31
4.4 Serial Digital Loop-Through Output ........................................................................................ 32
4.5 Serial Digital Reclocker ............................................................................................................... 32
4.5.1 PLL Loop Bandwidth ........................................................................................................ 33
4.6 External Crystal/Reference Clock ........................................................................................... 33
4.7 Lock Detect ...................................................................................................................................... 35
4.7.1 Asynchronous Lock .......................................................................................................... 35
4.7.2 Signal Interruption............................................................................................................ 36
4.8 SMPTE Functionality .................................................................................................................... 36
4.8.1 Descrambling and Word Alignment ........................................................................... 36
4.9 Parallel Data Outputs ................................................................................................................... 37
4.9.1 Parallel Data Bus Buffers................................................................................................. 37
4.9.2 Parallel Output in SMPTE Mode ................................................................................... 40
4.9.3 Parallel Output in DVB-ASI Mode ............................................................................... 40
4.9.4 Parallel Output in Data-Through Mode ..................................................................... 41
4.9.5 Parallel Output Clock (PCLK)......................................................................................... 41
4.9.6 DDR Parallel Clock Timing ............................................................................................. 42
4.10 Timing Signal Generator ........................................................................................................... 44
4.10.1 Manual Switch Line Lock Handling.......................................................................... 45
4.10.2 Automatic Switch Line Lock Handling .................................................................... 46
4.10.3 Switch Line Lock Handling During Level B to Level A Conversion ............... 46
4.11 Programmable Multi-function Outputs ............................................................................... 48
4.12 H:V:F Timing Signal Generation ............................................................................................ 50
4.12.1 CEA-861 Timing Generation ....................................................................................... 52
4.13 Automatic Video Standards Detection ................................................................................ 59
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
4 of 152