GS2971A Datasheet, PDF (147/152 Pages) Gennum Corporation – Integrated audio clock generator

5.3 Typical Application Circuit
Power Decoupling
+1.2V
+1.2V_A
10n
10n
10n
10n
10n
10n
10n
IO_VDD
A_GND
+3.3V_A
10n
10n
10n
10n
10n
10n
10n
Place close to GS2971A
A_GND
Place close to GS2971A
+1.2V_A
R7
105R
C18
33u
SMPTE_BY PASS
DVB_ASI
TIM_861
SW_EN
AUDIO_EN/DIS
IOPROC_EN/DIS
20BIT/10BIT
RC_BY P
JTAG/HOST
STANDBY
RESET_TRST
SDO_EN/DIS
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
Place close to GS2971A
A_GND
+1.2V_A
+3.3V_A
+1.2V
IO_VDD
A_GND
DNP
1u
47n
+3.3V_A
R19
DNP
A3 _{LB_CONT}
A1 _VBG
A2 _LF
B3 _RSV
TP
16p
H6 _{XTAL_OUT}
J6 _XTAL2
16p CS10-27.000M
K6 _XTAL1
CD_DISABLEb
G7
G8
H5
D7
SMPTE_BY PASS
DVB_ASI
TIM_861
SW_EN
H3
H8
H7
G3
D8
K2
C7
J2
AUDIO_EN/DIS
IOPROC_EN/DIS
20BIT/10BIT
RC_BY P
JTAG/HOST
STANDBY
RESET_TRST
SDO_EN/DIS
E7
E8
F8
F7
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
F2 _RSV
GS2971A-IBE3
STAT2
STAT1
STAT0
B5
A6
A5
PCLK ^A8
DOUT 19
DOUT 18
DOUT 17
B8
A9
A10
DOUT 16
DOUT 15
DOUT 14
DOUT 13
B9
B10
C9
C10
DOUT 12
DOUT 11
DOUT 10
C8
E10
E9
DOUT 9 ^F10
DOUT 8
DOUT 7
DOUT 6
DOUT 5
F9
H10
H9
J10
DOUT 4
DOUT 3
DOUT 2
DOUT 1
DOUT 0
J9
K10
K9
J8
K8
STAT3
STAT4
STAT5
B6
C5
C6
AMCLK ^K4
ACLK
WCLK
J4
H4
AOUT_1/2
AOUT_3/4
J3
K3
AOUT_5/6
AOUT_7/8
J5
K5
+3.3V
Power Filtering
CD_VDD +1.2V
0R
0R
10n
1u
1u
10n
10n
1u
+1.2V_A
1u
10n
0R
10n
1u
0R
A_GND
+3.3V_A
1u
10n
A_GND
IO_VDD
A_GND
1u
22R
22R
22R
F/DE (DEFAULT, PROGRAMMABLE)
V/VSY NC (DEFAULT, PROGRAMMABLE)
H/HSY NC (DEFAULT, PROGRAMMABLE)
22R
PCLK
DOUT[19:0]
DOUT[19:0]
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
LOCKED (DEFAULT, PROGRAMMABLE)
Y /1ANC (DEFAULT, PROGRAMMABLE)
DATA_ERRORb (DEFAULT, PROGRAMMABLE)
22R
22R
22R
AUDIO MASTER CLOCK
AUDIO SERIAL BIT CLOCK
AUDIO WORD CLOCK
AUDIO OUTPUT CH 1 & 2
AUDIO OUTPUT CH 3 & 4
AUDIO OUTPUT CH 5 & 6
AUDIO OUTPUT CH 7 & 8
6n2
UCBBJE20-1
1
75R
A_GND
75R
1u
1u
37R4
A_GND
470n
A_GND
F1 _AGCP
470n
G1 _AGCN
C1 _SDI
D1 _SDI
A_GND
SDO
SDO
K1
J1 ^A_GND
Close to
pin 1 & 2
of GS2978
10n
49R9
1 _SDI
SDO ¹²
49R9
2 _{SDI GS2978-CNE3 SDO} 11
3 _VEE
SD/HD ¹⁰
4
A_GND
RSET
VCC ⁹
750R
CD_VDD
CD_DISABLEb
10n
A_GND
75-ohm Traces
4u7
75R
75R ^CD_VDD
A_GND
10n
75R
5n6
A_GND
UCBBJE20-1
1
4u7
75R
CD SLEW RATE SELECT
CD_VDD
A_GND
Notes:
1. DNP (Do Not Populate).
2. The value of the series resistors on video data, clock, and timing
connections should be determined by board signal integrity test.
3. For analog power and ground isolation refer to PCB layout guide.
4. For critital 3G signal layout refer to PCB layout guide.
5. For impedance controlled signal layout refer to PCB layout guide.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
147 of 152