GS2971A Datasheet, PDF (116/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
403h
AUD_DET
IDB_READBACK
IDA_READBACK
XDPG4_DET
XDPG3_DET
XDPG2_DET
XDPG1_DET
ADPG4_DET
ADPG3_DET
ADPG2_DET
ADPG1_DET
ACS_APPLY_WAITD
ACS_APPLY_WAITC
ACS_APPLY_WAITB
ACS_APPLY_WAITA
404h
405h
CSUM_ERR_DET
RSVD
CSUM_ERROR
CH_MUTE
RSVD
MUTE
Bit Description
15-14
13-12
11
10
9
8
7
6
5
4
3
2
1
0
15-1
0
15-8
7-0
Actual value of IDB in the
hardware.
Actual value of IDA in the
hardware.
Set while embedded Group 4
audio extended packets are
detected.
Set while embedded Group 3
audio extended packets are
detected.
Set while embedded Group 2
audio extended packets are
detected.
Set while embedded Group 1
audio extended packets are
detected.
Set while Group 4 audio data
packets are detected.
Set while Group 3 audio data
packets are detected.
Set while Group 2 audio data
packets are detected.
Set while Group 1 audio data
packets are detected.
Set while output channels 7 and 8
are waiting for a status boundary
to apply the ACSR[183:0] data.
Set while output channels 5 and 6
are waiting for a status boundary
to apply the ACSR[183:0] data.
Set while output channels 3 and 4
are waiting for a status boundary
to apply the ACSR[183:0] data.
Set while output channels 1 and 2
are waiting for a status boundary
to apply the ACSR[183:0] data.
Reserved.
Embedded packet checksum error
detected. Write ’1’ to clear.
Reserved.
Mute output channels 8..1 Where
bits 7:0 = channel 8:1
1: Mute
0: Normal
R/W
R
Default
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R/W
0
ROCW
0
R/W
0
R/W
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
116 of 152