GS2971A Datasheet, PDF (142/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-29:HD and 3G Audio Core Configuration and Status Registers (Continued)
Address
28Eh
Register Name Bit Name
ACSR_BYTE_14
RSVD
ACSR14
28Fh
ACSR_BYTE_15
RSVD
ACSR15
290h
ACSR_BYTE_16
RSVD
ACSR16
291h
ACSR_BYTE_17
RSVD
ACSR17
292h
ACSR_BYTE_18
RSVD
ACSR18
293h
ACSR_BYTE_19
RSVD
ACSR19
294h
ACSR_BYTE_20
RSVD
ACSR20
Bit
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
Description
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
R/W
R/W
W
Default
0
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
142 of 152