GS2971A Datasheet, PDF (30/152 Pages) Gennum Corporation – Integrated audio clock generator

September 2012
54311 - 2
Data Sheet
30 of 152
GS2971A 3Gb/s, HD, SD SDI Receiver
“double” TRS headers from
interleaved HD-SDI;
Figure 4-2:Level B Mapping
multiplexed Y/C data
Active Video
Data Stream 1
(”Link A”)
EAV
Data Stream 2
(”Link 2”)
SAV
HANC
Figure 4-1:Level A Mapping
4.2.2 Level B Mapping
The 2 x 292 HD SDI interface - this can be two distinct links running at 1.5Gb/s or one
3Gb/s link formatted according to SMPTE 292 on two 10-bit links (Y/C interleaved). For
1080p/50/59.94/60 4:2:2 video formats, each link should be line-interleaved as per
SMPTE 372M. See Figure 4-2:
Data Stream 1
EAV
Data Stream 2
Active Video
SAV
HANC
NOTE: for 3Gb/s 10-bit mode the device operates in Dual Data Rate (DDR) mode, where
the data is sampled at both the rising and falling edges of the clock. This reduces the I/O
speed requirements of the downstream devices.
Up to eight channels, in two groups, of serial digital audio may be extracted from the
video data stream, in accordance with SMPTE 272M and SMPTE 299M. The output signal
formats supported by the device include AES/EBU and three other industry standard
serial digital formats. 16, 20 and 24-bit audio formats are supported at 48kHz
synchronous for SD modes and 48kHz synchronous or asynchronous in HD/3G mode.
Additional audio processing features include group selection, channel swapping, ECC
error detection and correction (HD mode only), and audio channel status extraction.
Audio clock and control signals provided by the device include Word Clock (fs), Serial
Clock (64fs), and Audio Master Clock at user-selectable rates of 128fs, 256fs or 512fs.
4.2 SMPTE 425M Mapping - 3G Level A and Level B Formats
4.2.1 Level A Mapping
Direct image format mapping - the mapping structure used to define 1080p/50/59.94/60
4:2:2 YCbCr 10 bit data, as supported by the GS2971A. See Figure 4-1: