GS2971A Datasheet, PDF (141/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-29:HD and 3G Audio Core Configuration and Status Registers (Continued)
Address
287h
Register Name Bit Name
ACSR_BYTE_7
RSVD
ACSR7
288h
ACSR_BYTE_8
RSVD
ACSR8
289h
ACSR_BYTE_9
RSVD
ACSR9
28Ah
ACSR_BYTE_10
RSVD
ACSR10
28Bh
ACSR_BYTE_11
RSVD
ACSR11
28Ch
ACSR_BYTE_12
RSVD
ACSR12
28Dh
ACSR_BYTE_13
RSVD
ACSR13
Bit
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
15-8
7-0
Description
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
Reserved.
Audio channel status to use when
ACS_REGEN is set or when adding
audio channel status to
non-AES/EBU audio. 8 bits per
register starting at register 280h
and ending at register 296h.
R/W
R/W
W
Default
0
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
R/W
0
W
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
141 of 152