GS2971A Datasheet, PDF (72/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-14:SMPTE 352M Packet Data
Bit Name
VIDEO_FORMAT_4_DS1
Address: 01Ah
VIDEO_FORMAT_3_DS1
Address: 01Ah
VIDEO_FORMAT_2_DS1
Address: 019h
VIDEO_FORMAT_2_DS1
Address: 019h
Bit
Name
15-8 SMPTE 352M
Byte 4
7-0 SMPTE 352M
Byte 3
15-8 SMPTE 352M
Byte 2
7-0 SMPTE 352M
Byte 1
Description
R/W
R
Default
0
R
0
Data is available in this register when Video Payload
Identification Packets are detected in the data
stream.
R
0
R
0
4.17.2.2 3G SMPTE 352M Packets Following Level B to Level A Conversion
After Level B to Level A conversion, modified payload data must be programmed via the
host interface into the VIDEO_FORMAT_352_X_X registers and automatically inserted
by the GS2971A on the correct SMPTE 352M Line Number.
SMPTE 352M Packets are embedded in both data streams.
Previously embedded 352M packets may be deleted from one data stream only (using
the ANC_DATA_DELETE bit, see Section 4.18.8), but these packets are replaced with
10-bit Y/C blanking values.
NOTE: Pre-existing SMPTE 352M Packets that are not deleted are re-mapped to
different line numbers during conversion to Level A formatting. These packets should be
ignored by the system, since they are on non-standard SMPTE 352M lines.
4.17.3 Ancillary Data Checksum Error
The GS2971A calculates checksums for all received ancillary data.
These calculated checksums are compared with the received ancillary data checksum
words.
If a mismatch in the calculated and received checksums is detected, then a checksum
error is indicated.
When operating in HD mode, the device makes comparisons on both the Y and C
channels separately. If an error condition in the Y channel is detected, the YCS_ERR bit
in the VIDEO_ERROR_STAT_X register is set HIGH. If an error condition in the C channel
is detected, the CCS_ERR bit in the VIDEO_ERROR_STAT_X register is set HIGH.
When operating in 3G Level A mode, the device makes comparisons on both the Y (Data
Stream 1) and C (Data Stream 2) channels separately. If an error condition in the Y
channel is detected, the YCS_ERR bit in the VIDEO_ERROR_STAT_X register is set HIGH.
If an error condition in the C channel is detected, the CCS_ERR bit in the
VIDEO_ERROR_STAT_X register is set HIGH.
When operating in 3G Level B mode, the device makes comparisons on both the Y
channel and the C channel of both Link A and Link B.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
72 of 152