GS2971A Datasheet, PDF (31/152 Pages) Gennum Corporation – Integrated audio clock generator

The GS2971A distinguishes between Level A and Level B mappings at 3Gb/s. When
Level B data is detected, each 10-bit link is demultiplexed into its individual component
streams, and most video processing features, including error detection and correction
are enabled separately for Data Stream 1 and Data Stream 2 (Link A and Link B,
respectively). Note that audio demultiplexing and ancillary data extraction can only be
enabled for one link for 3Gb/s Level B data. Data Stream 1 or Data Stream 2 can be
selected via the host interface.
4.3 Serial Digital Input
The GS2971A can accept serial digital inputs compliant with SMPTE 424M, SMPTE 292
and SMPTE 259M-C.
4.3.1 Integrated Adaptive Cable Equalizer
The GS2971A integrates Gennum's adaptive cable equalizer technology.
The integrated adaptive equalizer can equalize 3Gb/s, HD and SD serial digital signals,
and will typically equalize 150m of Belden 1694A cable at 2.97Gb/s, 250m at 1.485Gb/s
and 480m at 270Mb/s.The integrated adaptive equalizer is powered from a single +3.3V
power supply and consumes approximately 195mW of power.
The equalizer can be bypassed by programming register 073h through the GSPI
interface.
4.3.1.1 Serial Digital Inputs
The Serial Data Signal may be connected to the input pins (SDI/SDI) in either a
differential or single ended configuration. AC coupling of the inputs is recommended, as
the SDI and SDI inputs are internally biased at approximately 1.8V.
4.3.1.2 Cable Equalization
The input signal passes through a variable gain equalizing stage whose frequency
response closely matches the inverse of the cable loss characteristic. In addition, the
variation of the frequency response with control voltage imitates the variation of the
inverse cable loss characteristic with cable length.
The edge energy of the equalized signal is monitored by a detector circuit which
produces an error signal corresponding to the difference between the desired edge
energy and the actual edge energy. This error signal is integrated by both an internal and
an external AGC filter capacitor providing a steady control voltage for the gain stage. As
the frequency response of the gain stage is automatically varied by the application of
negative feedback, the edge energy of the equalized signal is kept at a constant level
which is representative of the original edge energy at the transmitter. The equalized
signal is also DC restored, effectively restoring the logic threshold of the equalized signal
to its correct level independent of shifts due to AC coupling.
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
31 of 152