GS2971A Datasheet, PDF (119/152 Pages) Gennum Corporation – Integrated audio clock generator

Table 4-28:SD Audio Core Configuration and Status Registers (Continued)
Address Register Name Bit Name
408h
CFG_OUTPUT ASWLD
ASWLC
ASWLB
ASWLA
AMD
409h
AMC
AMB
AMA
OUTPUT_SEL_1
RSVD
OP4_SRC
OP3_SRC
OP2_SRC
OP1_SRC
Bit Description
15-14
13-12
11-10
9-8
7-6
5-4
3-2
1-0
15-12
11-9
8-6
5-3
2-0
Output channels 7 and 8 word
length.
00: 24 bits
01: 20 bits
10: 16 bits
11: Automatic 20-bit or 24-bit
Output channels 5 and 6 word
length. (See above for decoding)
Output channels 3 and 4 word
length. (See above for decoding)
Output channels 1 and 2 word
length. (See above for decoding)
Output channels 7 and 8 format
selector.
00: AES/EBU audio output
01: Serial audio output: Left
justified; MSB first
10: Serial audio output: Right
justified; MSB first
11: I²S serial audio output
Output channels 5 and 6 format
selector. (See above for decoding).
Output channels 3 and 4 format
selector. (See above for decoding).
Output channels 1 and 2 format
selector. (See above for decoding).
Reserved.
Output channel 4 source selector.
000: Primary audio group channel
1
001: Primary audio group channel
2
010: Primary audio group channel
3
011: Primary audio group channel
4
100: Secondary audio group
channel 1
101: Secondary audio group
channel 2
110: Secondary audio group
channel 3
111: Secondary audio group
channel 4
Output channel 3 source selector
(Decode as above).
Output channel 2 source selector
(Decode as above).
Output channel 1 source selector
(Decode as above).
R/W
R/W
Default
3
R/W
3
R/W
3
R/W
3
R/W
3
R/W
3
R/W
3
R/W
3
R/W
0
R/W
3
R/W
2
R/W
1
R/W
0
GS2971A 3Gb/s, HD, SD SDI Receiver
Data Sheet
54311 - 2
September 2012
119 of 152