MB81P643287 Datasheet, PDF (6/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
s FUNCTION TRUTH TABLE (Note*1)
COMMAND TRUTH TABLE (Note *2, and *3)
Function
Notes Symbol CKE CS RAS CAS WE BA2-0 A10/AP A9-7 A6-0
Device Deselect
*4 DESL H H X X X X
X
XX
No Operation
*4 NOP H L H H H X
X
XX
Burst Stop
*5 BST H L H H L X
X
XX
Read
*6 READ H L H L H V
L
XV
Read with Auto-precharge
*6 READA H L H L H V
H
XV
Write
*6 WRIT H L H L L V
L
XV
Write with Auto-precharge
*6 WRITA H L H L L V
H
XV
Bank Active (RAS)
*7 ACTV H L L H H V
V
VV
Precharge Single Bank
*8 PRE H L L H L V
L
XX
Precharge All Banks
*8 PALL H L L H L V
H
XX
Mode Register Set/
Extended Mode Register Set
*8,9,10
MRS/
EMRS
H
L
L
L
L
V
L
VV
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance.
*2. All commands are assumed to be valid state transitions.
*3. All inputs for command are latched on the rising edge of clock(CLK).
*4. NOP and DESL commands have the same effect on the part.
Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions.
*5. BST is effective after READ command is issued.
*6. READ, READA, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to “s STATE DIAGRAM”.
*7. ACTV command should only be issued after corresponding bank has been page closed by PRE or
PALL command.
*8. Either PRE or PALL command and MRS or EMRS command are required after power up.
*9. MRS or EMRS command should only be issued after all banks have been page closed (PRE or PALL
command), and DQs are in Hi-Z. Refer to “s STATE DIAGRAM”.
*10. Refer to“s MODE REGISTER TABLE”.
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