MB81P643287 Datasheet, PDF (47/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 9: READ INTERRUPTED BY BURST STOP
(EXAMPLE @ CL = 2, BL = 8)
CLK
CLK
Command
READ
DQS (Output) ^Hi-Z
DQ0 to DQ31 Hi-Z
(Output)
BST
NOP
IBSH ( = CAS Latency)
Q1 Q2
Command
READ
NOP
DQS (Output) ^Hi-Z
DQ0 to DQ31 ^Hi-Z
(Output)
BST
NOP
IBSH ( = CAS Latency)
Q1 Q2 Q3 Q4
Command
READ
Hi-Z
DQS (Output)
DQ0 to DQ31 Hi-Z
(Output)
NOP
BST
NOP
IBSH ( = CAS Latency)
Q1 Q2 Q3 Q4 Q5 Q6
Command
READ
Hi-Z
DQS (Output)
NOP
BST
NOP
No effect (End of Burst)
DQ0 to DQ31 Hi-Z
(Output)
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Note: lBSH is the same as CAS Latency (CL). In case of CL =3, the lBSH is 3 clock.
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