MB81P643287 Datasheet, PDF (38/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
Fig. 5 - AC TEST LOAD CIRCUIT (SSTL_2, Class II)
VTT = 0.5 × VDDQ
Output
measure-
ment
point
RT1 = 50 Ω
Output
VDDQ
RS = 25 Ω
VDDQ
Z0 = 50 Ω
VREF
0.5 × VDDQ
Device
Under
Test
VTT = 0.5 × VDDQ
RT2 = 50 Ω
VREF = 0.5 × VDDQ
CL = 20 pF
VSS
Note: AC characteristics are measured in this condition. This load circuit is not applicable for DC Test.
AC TEST CONDITIONS
Parameters
Single-end Input
Input High Level
Input Low Level
Input Reference Level
Input Slew Rate
Differential Input (CLK and CLK)
Input Reference Level
Input Level
Input Slew Rate
Symbol
VIH
VIL
VREF
SLEW
Vr
VSWING
SLEW
* : VX means the actual cross point between CLK and CLK input.
Value
VREF + 0.35
VREF − 0.35
VDDQ / 2
1.0
VX (AC)*
0.7
1.0
Unit
V
V
V
V/ns
V
V
V/ns
38