MB81P643287 Datasheet, PDF (25/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields; Burst Length, Burst Type, CAS Latency, and Test Mode Entry (This Test Mode Entry must not be used).
Refer to MODE REGISTER TABLE.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-programmed
by another MRS command (or part loses power). MRS command should only be issued on condition that all
banks are in idle state and all DQS are in High-Z. The condition of the mode register is undefined after the power-
up stage. It is required to set each field at power-up initialization.
Refer to POWER-UP INITIALIZATION below.
Note: The Extended Mode Register Set command (EMRS) and its DLL Enable function of EMRS field is only used
at power-on sequence.
POWER-UP INITIALIZATION
The MB81P643287 internal condition at and after power-up will be undefined. It is required to follow the following
Power On Sequence to execute read or write operation.
1. Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins and attempt to maintain all input
signals to be Low state (or at least CKE to be Low state).
2. Apply VDD voltage to all VDDQ pins before or at the same time as VREF and VTT.
3. Apply VREF and VTT. (VTT is applied to the system).
4. Start clock after all power supplies reached in a specified operating range and maintain stable condition
for a minimum of 200 µs.
5. After the minimum of 200 µs stable power and clock, apply NOP condition and take CKE to be High
state.
6. Issue Precharge All Banks (PALL) command or Precharge Single Bank (PRE) command to every
banks.
7. Issue EMRS to enable DLL, DE = Low.
8. Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for lPCD*¹
period is required to lock the DLL.
9. Apply minimum of two Auto-refresh command (REF).*²
10. Program the mode register by Mode Register Set command (MRS) with DR = Low.*²
*1: The lPCD depends on operating clock period. The lPCD is counted from “DLL Reset” at step-8 to any command
input at step-10.
*2: The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
POWER-DOWN
The MB81P643287 uses multiple power supply voltage. It is required to follow the reversed sequence of above
Power On Sequence.
1. Take all input signals to be VSS or High-Z.
2. Deapply VDDQ.
3. Deapply VDD at the same time as VDDQ.
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