MB81P643287 Datasheet, PDF (49/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 12: READ TO WRITE (EXAMPLE @ CL = 2, BL = 4)
CLK
CLK
Command
DQS
Hi-Z
READ
BST
lBSNC
NOP
lBSH
WRIT
tDQSS
NOP
DM
Don't Care
Hi-Z
DQ0 to DQ31
Q1 Q2
D1 D2 D3 D4
Terminated
Note: DM are latched by DQS Input after Write command together with data Input.
TIMING DIAGRAM - 13: WRITE TO READ (EXAMPLE @ CL = 2, BL = 8)
CLK
CLK
Command
DQS
Hi-Z
WRIT
tDQSS
NOP
lWRD
READ
NOP
CL
DM
Don't Care
DQ0 to DQ31
D1 D2
Hi-Z
Q1 Q2
Masked
Terminated by Read
Note: Read command must be issued after lWRD is satisfied and proceeding pair of data must be masked.
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