MB81P643287 Datasheet, PDF (50/65 Pages) Fujitsu Component Limited. – 8 x 256K x 32 BIT, FCRAMTM CORE BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60
TIMING DIAGRAM - 14: READ WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2, BL = 4, Multiple Bank Operation)
CLK
CLK
BL
2
×
tCK
+
lRP
lRP (Min.)
lRCD (Min.)
Command
READA
PRE
READA READA
ACTV
lCBD
lCBD
lCBD
lCBD
lRRD (Min.)
ACTV
READ
lCBD
BA0, BA1
Bank 0 Bank 1 Bank 2
DQS (Output) ^Hi-Z
CAS Latency
Bank 3
Bank 1
Bank 0 Bank 1
Hi-Z
DQ0 to DQ31
(Output)
Q1 Q2 Q3 Q4 Q1 Q2 Q1 Q2 Q3 Q4
Note: Back to back Read with Auto-precharge (READA) command to the different bank in active state
is possible. However, any new command to the same bank applied READA command can only
be issued after (BL/2) × tCK+lRP.
CLK
CLK
Command
BA0, BA1
DQS (Input)
TIMING DIAGRAM - 15: WRITE WITH AUTO-PRECHARGE
(EXAMPLE @ CL = 2, BL = 4, Multiple Bank Operation)
lWAL (Min.)
WRITA WRITA
PRE
WRITA
lCBD (Min.) lCBD (Min.) lCBD (Min.)
lRP (Min.)
Bank 0 Bank 1 Bank 2
tDQSS
tDQSS
Bank 3
tDQSS
ACTV
ACTV
lRRD (Min.)
Bank 2
Bank 0
DQ0 to DQ31
(Input)
D1 D2 D1 D2 D3 D4 D1 D2 D3 D4
Note: Back to back Write with Auto-precharge (WRITA) command to the different bank in active state
is possible. However, any new command to the same bank applied WRITA command can only
be issued after lWAL.
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